MC14043BDR2

© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 6
1 Publication Order Number:
MC14043B/D
MC14043B, MC14044B
CMOS MSI
Quad R−S Latches
The MC14043B and MC14044B quad R−S latches are constructed
with MOS P−Channel and N−Channel enhancement mode devices in a
single monolithic structure. Each latch has an independent Q output
and set and reset inputs. The Q outputs are gated through three−state
buffers having a common enable input. The outputs are enabled with a
logical “1” or high on the enable input; a logical “0” or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs.
Features
Double Diode Input Protection
Three−State Outputs with Common Enable
Outputs Capable of Driving Two Low−power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature Range
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage Range 0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
0.5 to V
DD
+ 0.5 V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
± 10 mA
P
D
Power Dissipation, per Package
(Note 1)
500 mW
T
A
Ambient Temperature Range 55 to +125 °C
T
stg
Storage Temperature Range 65 to +150 °C
T
L
Lead Temperature
(8−Second Soldering)
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v (V
in
or V
out
) v V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
MC140xxBCP
AWLYYWWG
SOIC−16
D SUFFIX
CASE 751B
140xxBG
AWLYWW
xx = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Indicator
SOEIAJ−16
F SUFFIX
CASE 966
MC140xxB
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
16
1
1
16
1
16
MC14043B, MC14044B
http://onsemi.com
2
MC14043B
TRUTH TABLE
X = Don’t Care
MC14044B
SRE Q
High
Impedance
XX0
No Change
0
1
1
0
0
1
1
0
1
0
1
1
1
1
1
TRUTH TABLE
X = Don’t Care
S R EQ
High
Impedance
XX0
0
1
0
No Change
0
0
1
1
0
1
0
1
1
1
1
1
ENABLE
R3
S3
R2
S2
R1
S1
R0
S0
4
3
6
7
12
11
14
15
5
Q3
Q2
Q1
Q0
2
9
10
1
ENABLE
S3
R3
S2
R2
S1
R1
S0
R0
4
3
6
7
12
11
14
15
5
Q3
Q2
Q1
Q0
13
9
10
1
V
DD
= PIN 16
V
SS
= PIN 8
NC = PIN 2
V
DD
= PIN 16
V
SS
= PIN 8
NC = PIN 13
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
S2
NC
S3
R3
V
DD
Q1
Q2
R2
S0
R0
Q0
Q3
V
SS
R1
S1
E
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
R2
Q0
R3
S3
V
DD
Q1
Q2
S2
R0
S0
NC
Q3
V
SS
S1
R1
E
NC = NO CONNECTION
MC14043B MC14044B
MC14043B, MC14044B
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
Characteristic Symbo
l
V
DD
Vdc
− 55_C 25_C 125_C
Unit
Min Max Min Typ
(Note 2)
Max Min Max
Output Voltage “0” Leve
l
V
in
= V
DD
or 0
“1” Leve
l
V
in
= 0 or V
DD
V
OL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
V
OH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage “0” Leve
l
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Leve
l
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
V
IL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
Vdc
V
IH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc) Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc) Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
– 1.7
– 0.36
– 0.9
– 2.4
mAdc
I
OL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current I
in
15 ± 0.1 ± 0.00001 ± 0.1 ± 1.0
mAdc
Input Capacitance
(V
in
= 0)
C
in
5.0 7.5 pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
1.0
2.0
4.0
0.002
0.004
0.006
1.0
2.0
4.0
30
60
120
mAdc
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs all
buffers switching)
I
T
5.0
10
15
I
T
= (0.58 mA/kHz) f + I
DD
I
T
= (1.15 mA/kHz) f + I
DD
I
T
= (1.73 mA/kHz) f + I
DD
mAdc
Three−State Output Leakage
Current
I
TL
15 ± 0.1 ± 0.0001 ± 0.1 ± 3.0
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
− 50) Vfk
where: I
T
is in mA (per package), C
L
in pF, V = (V
DD
− V
SS
) in volts, f in kHz is input frequency, and k = 0.004.

MC14043BDR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Latches 3-18V Quad R-S
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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