MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
PIN
Supply Output for CMOS RAM. When V
CC
rises above the reset threshold or above
V
BATT
, OUT is connected to V
CC
through an internal p-channel MOSFET switch. When
V
CC
falls below V
SW
and V
BATT
, BATT connects to OUT.
OUT1 1
Reset Input. Connect to an external resistor-divider to select the reset threshold. The
reset threshold can be programmed anywhere in the V
SW
to 5.5V range.
RESET IN
(MAX794)
3 —
Battery Status Output. High in normal operating mode when V
BATT
exceeds V
BOK
, other-
wise low. V
BATT
is checked continuously. Disabled and logic low while V
CC
is below V
SW
.
BATT OK
(MAX793)
Main Supply InputV
CC
2 2
Power-Fail Comparator Output. When PFI is less than V
PFT
or when V
CC
falls below
V
SW
, PFO goes low; otherwise, PFO remains high. PFO is also used to enable the bat-
tery freshness seal (see
Battery Freshness Seal
and
Power-Fail Comparator
sections).
PFO
7 —
Active-High Reset Output. Sources and sinks current. RESET is the inverse of RESET.
RESET13
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted.
If CE IN is low when reset is asserted, CE OUT remains low for 10µs or until CE IN goes
high, whichever occurs first. CE OUT is pulled up to OUT.
CE OUT
12
—
6
GroundGND6
Power-Fail Comparator Input. When PFI is less than V
PFT
or when V
CC
falls below V
SW
,
PFO goes low; otherwise, PFO remains high (see
Power-Fail Comparator
section).
Connect to V
CC
if unused.
PFI4
Chip-Enable Input. The input to the chip-enable gating circuit. Connect to GND if unused.
CE IN
11 5
4
—
Watchdog Output. WDO goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO returns high on the next transition of WDI. WDO is a
logic high for V
SW
< V
CC
< V
RST
, and low when V
CC
is below V
SW
.
WDO
9 —
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as
MR is low and for 200ms after MR returns high. The active-low input has an internal
70µA pullup current. It can be driven from a TTL- or CMOS-logic line or shorted to
ground with a switch. Leave open if unused.
MR
8 —
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
period, the internal watchdog timer runs out and WDO goes low. WDO returns high on
the next transition of WDI. Connect WDO to MR to generate a reset due to a watchdog
fault.
WDI10 —
Early Power-Fail Warning Output. Low when V
CC
falls to V
LR
. This output can be used to
generate an NMI to provide early warning of imminent power failure.
LOWLINE
14 —
Open-Drain, Active-Low Reset Output. Pulses low for 200ms when triggered, and stays
low whenever V
CC
is below the reset threshold or when MR is a logic low. It remains low
for 200ms after either V
CC
rises above the reset threshold, the watchdog triggers a reset
(WDO connected to MR), or MR goes low to high.
RESET
15 7
Backup-Battery Input. When V
CC
falls below V
SW
and V
BATT
, OUT switches from V
CC
to
BATT. When V
CC
rises above the reset threshold or above V
BATT
, OUT reconnects to
V
CC
. V
BATT
can exceed V
CC
. Connect V
CC
, OUT, and BATT together if no battery is
used.
BATT16 8
Logic Output/External Bypass Switch-Driver Output. High when OUT switches to BATT.
Low when OUT switches to V
CC
. Connect the base/gate of PNP/PMOS transistor to
BATT ON for I
OUT
requirements exceeding 75mA.
BATT ON5 3
MAX793/
MAX794
FUNCTIONNAME
MAX795
