MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
4 _______________________________________________________________________________________
CONDITIONS
V
OL
V
V
OL
VI
SINK
= 3.2mA, V
CC
= V
RST
max
MAX79_E, V
BATT
= V
CC
= 1.2V, I
SINK
= 200µA
BATT ON Output-
Voltage Low
MAX79_C, V
BATT
= V
CC
= 1.0V, I
SINK
= 40µA
0.2V
CC
RESET Output-Voltage Low
UNITSMIN TYP MAXSYMBOLPARAMETER
V
IL
V
t
MR
nsMAX793/MAX794 only
V
RST
max < V
CC
< 5.5V
MR Pulse Width
100
All Inputs Including PFO
(Note 10)
0.3V
CC
V
IH
0.7V
CC
0.17 0.3
0.13 0.3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.17V to 5.5V for the MAX793T/MAX795T, V
CC
= 3.02V to 5.5V for the MAX793S/MAX795S, V
CC
= 2.72V to 5.5V for the
MAX793R/MAX794/MAX795R, V
BATT
= 3.6V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
t
MD
ns
MAX793/MAX794 only, MR = 0V
MAX793/MAX794 only
µA
MR-to-Reset Delay
25 70 250
MR Pullup Current
75 250
Ω
nsV
CC
= V
RST
max, Figure 9
Enable mode, V
CC
= V
RST
max
CE IN-to-CE OUT
Propagation Delay
Disable mode
27
CE IN-to-CE OUT
Resistance
V
OH
V
OL
V
V
CC
= V
RST
max, I
OUT
= 1.6mA,
V
CE IN
= 0V
V
CC
= V
RST
max, I
OUT
= -1mA,
V
CE IN
= V
CC
CE OUT Drive from CE IN
0.2V
CC
0.8V
CC
nA
46
I
LEAK
±10
CE IN Leakage Current
Note 1: V
CC
supply current, logic-input leakage, watchdog functionality (MAX793/MAX794), MR functionality (MAX793/MAX794),
PFI functionality (MAX793/MAX794), and state of RESET and RESET (MAX793/MAX794) tested at V
BATT
= 3.6V and V
CC
=
5.5V. The state of RESET is tested at V
CC
= V
CC
min.
Note 2: Tested at V
BATT
= 3.6V, V
CC
= 3.5V and 0V. The battery current rises to 10µA over a narrow transition window around V
CC
= 1.9V.
Note 3: Leakage current into the battery is tested under the worst-case conditions at V
CC
= 5.5V, V
BATT
= 1.8V and V
CC
= 1.5V,
V
BATT
= 1.0V.
Note 4: Guaranteed by design.
Note 5: When V
SW
> V
CC
> V
BATT
, OUT remains connected to V
CC
until V
CC
drops below V
BATT
. The V
CC
-to-V
BATT
comparator
has a small 15mV typical hysteresis to prevent oscillation. For V
CC
< 1.75V (typical), OUT switches to BATT regardless of
V
BATT
.
Note 6: When V
BATT
> V
CC
> V
SW
, OUT remains connected to V
CC
until V
CC
drops below the battery switch threshold (V
SW
).
Note 7: OUT switches from BATT to V
CC
when V
CC
rises above the reset threshold, if V
BATT
> V
RST
. In this case, switchover back
to V
CC
occurs at the exact voltage that causes reset to be asserted, however, switchover occurs 200ms prior to reset. If
V
BATT
< V
RST
, OUT switches from BATT to V
CC
when V
CC
exceeds V
BATT
.
Note 8: The reset threshold tolerance is wider for V
CC
rising than for V
CC
falling to accommodate the 10mV typical hysteresis,
which prevents internal oscillation.
Note 9: The leakage current into or out of the RESET pin is tested with RESET not asserted (RESET output high impedance).
Note 10: PFO is normally an output, but is used as an input when activating the battery freshness seal.
µs10
Reset to CE OUT High Delay
t
WD
s
0V < V
CC
< 5.5V
Watchdog Timeout Period
I
OH
= 500µA, V
CC
< 2.3V
µA
1.00 1.60 2.25
-1 0.01 1WDI Input Current
VV
OH
0.8V
BATT
CE OUT Output-Voltage
High (reset active)
nsWDI Pulse Width 100
MANUAL RESET INPUT
CHIP-ENABLE GATING
WATCHDOG (MAX793/MAX794 only)
