96D2-2G800NN-TRL1

T
T
T
S
S
S
5
5
5
Q
Q
Q
N
N
N
U
U
U
2
2
2
9
9
9
8
8
8
0
0
0
0
0
0
-
-
-
5
5
5
S
S
S
240PIN DDR2 800 Unbuffered DIMM
2GB With 128Mx8 CL6
Transcend Information Inc.
SERIAL PRESENCE DETECT SPECIFICATION
Serial Presence Detect
Byte No.
Function Described Standard Specification
Vendor Part
0
# of Serial PD Bytes written during module production
128bytes 80
1 Total # of Bytes of S.P.D Memory Device 256bytes 08
2 Fundamental Memory Type DDR2 SDRAM 08
3 # of Row Addresses on this Assembly 14 0E
4 # of Column Addresses on this Assembly 10 0A
5 # of Module Rows on this Assembly
2 ROW, Planar,
18.3.0mm
01
6 Data Width of this Assembly 64bits 40
7
Reserved
- 00
8 VDDQ and Interface Standard of this Assembly SSTL 1.8V 05
9
DDR2 SDRAM cycle time at Max. Supported CAS
latency=X
2.50ns 25
10
DDR2 SDRAM Access time from clock at CL=X
0.40ns
40
11 DIMM configuration type (non-parity, Parity, ECC) Non ECC 00
12 Refresh Rate 7.8us 82
13 Primary DDR2 SDRAM Width X8 08
14 Error Checking DDR2 SDRAM Width N/A 00
15 Reserved - 00
16
DDR2 SDRAM device attributes: Burst lengths
supported
4,8 0C
17
DDR2 SDRAM device attributes: # of banks on each
DDR2 SDRAM device
8 banks 08
18
DDR2 SDRAM device attributes:CAS Latency
supported
6,5,4 70
19 DIMM Mechanical Characteristics X=< 4.10 01
20
DIMM type information
Regular UDIMM 02
21 DDR2 SDRAM Module Attributes
Analysis probe not
installed, FET switch
external not enable
00
22 DDR2 SDRAM Device Attributes: General Supports weak driver
07
23 DDR2 SDRAM Cycle Time CL=X-1 3.0ns 30
24 DDR2 SDRAM Access from Clock CL=X-1
0.45ns
45
25 DDR2 SDRAM Cycle Time CL=X-2 3.75ns 3D
26 DDR2 SDRAM Access from Clock CL=X-2
0.5ns
50
27 Minimum Row Precharge Time (tRP) 15ns 3C
28 Minimum Row Active to Row Activate delay (tRRD) 7.5ns 1E
29 Minimum RAS to CAS Delay (tRCD) 15ns 3C
30 Minimum active to Precharge time (tRAS) 45ns 2D
31 Module ROW density 1GB 01
32
Command and address setup time before clock(=tIS)
0.175ns 17
33
Command and address hold time after clock(=tIH)
0.25ns 25
34
Data input setup time before strobe(=tDS)
0.05ns 05
35
Data input hold time after strobe(=tDH)
0.125ns 12
36
Write recovery time(=tWR)
15ns 3C
T
T
T
S
S
S
5
5
5
Q
Q
Q
N
N
N
U
U
U
2
2
2
9
9
9
8
8
8
0
0
0
0
0
0
-
-
-
5
5
5
S
S
S
240PIN DDR2 800 Unbuffered DIMM
2GB With 128Mx8 CL6
Transcend Information Inc.
37
Internal write to read command delay(=tWTR)
7.5ns 1E
38
Internal read to precharge command delay(=tRTP)
7.5ns 1E
39
Memory analysis probe characteristics
- 00
40
Extension of Byte41 tRC and Byte42 tRFC
tRC(57.5ns) 06
41
DDR2 SDRAM Minimum Active to Active/Auto Refresh
Time(tRC)
60ns 3C
42
DDR2 SDRAM Minimum Auto-Refresh to
Active/Auto-Refresh Command Period (tRFC)
127.5ns 7F
43
DDR2 SDRAM Maximum Device Cycle Time (tCK
max)
8ns 80
44
DDR2 SDRAM DQS-
DQ Skew for DQS and associated
DQ signals (tDQSQ max)
0.20ns 14
45
DDR2 SDRAM Read Data Hold Skew Factor (tQHS)
0.3ns 1E
46
PLL Relock Time
- 00
47~61
Superset Information
- 00
62 SPD Data Revision Code REV 1.2 12
63 Checksum for Bytes 0-62 - 81
64-71 Manufacturers JEDEC ID Transcend 7F, 4F
72 Manufacturing Location T 54
54
53
32
35
36
4D
4C
51
36
34
56
38
73-90 Manufacturers Part Number TS5QNU29800-5S
55
20
20
20
20
20
91-92 Revision Code - -
93-94 Manufacturing Date By Manufacturer Variable
95-98 Assembly Serial Number By Manufacturer Variable
99-127
Manufacturer Specific Data - -
128~255
Open for customer use
Undefined -

96D2-2G800NN-TRL1

Mfr. #:
Manufacturer:
Advantech
Description:
Memory Modules 2G DDR2-800 240PIN 128X8 VLP SAM(G)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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