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DS1004Z-5+

P1-P3P4-P6
DS1004
4 of 6
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -1.0V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature See J-STD-020A Specification
Short Circuit Output Current 50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; V
CC
= 5.0V ± 5%)
PARAMETER SYM TEST
CONDITION
MIN TYP MAX UNITS NOTES
Supply Voltage V
CC
4.75 5.00 5.25 V 1
Active Current I
CC
V
CC
=5.25V
Period=1 µs
35 75 mA
High Level Input
Voltage
V
IH
2.2 V
CC
+ 0.5 V 1
Low Level Input
Voltage
V
IL
-0.5 0.8 V 1
Input Leakage I
I
0.0V ≤ V
I
≤ V
CC
-1.0 1.0 µA
High Level Output
Current
I
OH
V
CC
=4.75V
V
OH
=4V
-1.0 mA
Low Level Output
Current
I
OL
V
CC
=4.75V
V
OL
=0.5V
12 mA
AC ELECTRICAL CHARACTERISTICS (T
A
= 25°C; V
CC
= 5V ± 5%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Period t
PERIOD
4 (t
WI
)ns3
Input Pulse Width t
WI
40% of Tap 5 t
PLH
ns 3
Input to Tap 1
Output Delay
t
PLH
,
t
PHL
Table 1 ns 2
Tap-to-Tap Delays t
PLH
Table 1 ns 2
Output Rise or
Fall Time
t
OR
,
t
OF
2.0 2.5 ns
Power-up Time t
PU
100 ms
CAPACITANCE (T
A
= 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
IN
10 pF
DS1004
5 of 6
NOTES:
1. All voltages are referenced to ground.
2. V
CC
=5V and 25°C. Delay accuracy on both the rising and falling edges within tolerances given in
Table 1.
3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application
sensitive with respect to decoupling, layout, etc.
TEST CONDITIONS
INPUT:
Ambient Temperature: 25°C ±=3°C
Supply Voltage (V
CC
): 5.0V ±=0.1V
Input Pulse: High = 3.0V ±=0.1V
Low = 0.0V ±=0.1V
Source Impedance: 50 ohm max.
Rise and Fall Time: 3.0 ns max. (measured between 0.6V and 2.4V)
Pulse Width: 500 ns
Pulse Period: 1 µs
Output Load
Capacitance: 15 pF
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the devices under other data sheet conditions.
TIMING DIAGRAM: DS1004 INPUT TO OUTPUTS
DS1004
6 of 6
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
WI
(Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
RISE
(Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t
FALL
(Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
t
PLH
(Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the output pulse.
t
PHL
(Time Delay, Falling): The elapsed time between the 1.5V point on the falling edge of the input
pulse and the 1.5V point on the falling edge of the output pulse.
P1-P3P4-P6

DS1004Z-5+

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IC DELAY LINE 5TAP 25NS 8SOIC
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