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CAT1232LPW-T2

P1-P3P4-P6P7-P9P10-P11
CAT1232LP, CAT1832
Doc. No. MD-3018 Rev. F 4 © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
TYPICAL CHARACTERISTICS
For the CAT1232LP, V
CC
= 5 V and T
AM B
= 25ºC unless otherwise stated.
Threshold Voltage vs. Temperature (10% TOL) Threshold Voltage vs. Temperature (5% TOL)
4.610
4.615
4.620
4.625
4.630
-50 0 50 100
TEMPERATURE (ºC)
THRESHOLD VOLTAGE (V)
TOL = GND (5%)
Supply Current vs. Temperature Reset Active Time vs. Temperature
Reset Active Time Waveform Transient Response
4.430
4.435
4.440
4.445
4.450
-50 0 50 100
TEMPERATURE (°C)
THRESHOLD VOLTAGE (V)
TOL = Vcc (10%)
0
10
20
30
40
-50 0 50 100
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
Vcc = 4.5V
V
cc = 5.5V
300
400
500
600
700
800
-50 0 50 100
TEMPERATURE (°C)
RESET ACTIVE TIME (ms)
V
cc = 5.5V
V
cc = 4.5V
TD = open
CAT1232LP, CAT1832
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4
CAT1232LP, CAT1832
© 2009 SCILLC. All rights reserved. 5 Doc. No. MD-3018 Rev. F
Characteristics subject to change without notice
APPLICATION INFORMATION
SUPPLY VOLTAGE MONITOR
Reset Signal Polarity and Output Stage Structure
RESET
¯¯¯¯¯¯
is an active LOW signal. It is developed with
an open drain driver in the CAT1232LP. A pull-up
resistor is required, typical values are 10 kΩ to 50 kΩ.
The CAT1832 uses a CMOS push-pull output stage
for the RESET
¯¯¯¯¯¯
.
RESET is an active High signal developed by a
CMOS push-pull output stage and is the logical
opposite to RESET
¯¯¯¯¯¯
.
Trip Point Tolerance Selection
The TOL input is used to select the V
CC
trip point
threshold. This selection is made connecting the
TOL input to ground or V
CC
. Connecting TOL to
Ground makes the V
CC
trip threshold 4.62 V for the
CAT1232LP and 2.88 V for the CAT1832.
Connecting TOL to V
CC
makes the V
CC
trip threshold
4.37 V for the CAT1232LP and 2.55 V for the
CAT1832.
After V
CC
has risen above the trip point set by TOL,
RESET and RESET
¯¯¯¯¯¯
remain active for a minimum time
period of 250 ms.
On power-down, once V
CC
falls below the reset
threshold the RESET outputs will remain active and
are guaranteed valid down to a V
CC
level of 1.0 V.
Trip Point Voltage (V)
Tolerance
Select
Voltage
Trip Point
Tolerance
Min Nominal Max
CAT1232LP
TOL = V
CC
10 % 4.25 4.37 4.49
CAT1232LP
TOL = GND
5 % 4.50 4.62 4.74
CAT1832
TOL = V
CC
20 % 2.47 2.55 2.64
CAT1832
TOL = GND
10 % 2.80 2.88 2.97
Manual Reset Operation
Push-button input, PBRST
¯¯¯¯¯¯
, allows the user to issue
reset signals. The pushbutton input is debounced and
is pulled high through an internal 40 kΩ resistor.
When PBRST
¯¯¯¯¯¯
is held low for the minimum time of
20 ms, both resets become active and remain active
for a minimum time period of 250 ms after PBRST
returns high.
No external pull-up resistor is required, since PBRST
¯¯¯¯¯¯
is pulled high by an internal 40 kΩ resistor.
PBRST
¯¯¯¯¯¯
can be driven from a TTL or CMOS logic line
or short-ed to ground with a mechanical switch.
Figure 1. Timing Diagram: Power Up
Figure 2. Timing Diagram: Power Down
V
CCTP(MAX)
V
CCTP
V
CCTP(MIN)
V
CC
RESE
T
RESE
T
t
R
t
RPU
V
OH
V
OL
V
CCTP(MAX)
V
CCTP
V
CCTP(MIN)
V
CC
RESET
RESET
t
F
V
OH
V
OL
t
RPD
CAT1232LP, CAT1832
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5
CAT1232LP, CAT1832
Doc. No. MD-3018 Rev. F 6 © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
WATCHDOG TIMER AND ST
¯¯
INPUT
A watchdog timer stops and restarts a microprocessor
that has stopped proper operation or become “hung”.
The watchdog performs this function by monitoring the
ST
¯¯
input. After the reset outputs go inactive the ST
¯¯
input must be strobed with a high-to-low signal
transition prior to the minimum watchdog timeout
period. However if the ST
¯¯
input is not strobed with a
high-to-low signal transition prior to a watchdog
timeout the reset outputs will become active for TRST
reseting and restarting the microprocessor. Once the
resets return to the inactive state the watchdog timer
restarts the process.
The TD input allows the user to select from three
predetermined watchdog timeout periods. Always use
the minimum timeout period to determine the required
frequency of ST
¯¯
high-to-low transitions and the
maximum to determine the time prior to the reset
outputs becoming active. ST
¯¯
pulse widths must be
20 ns or greater.
The watchdog timer cannot be disabled. It must be
strobed with a high-to-low signal transition to avoid a
watchdog timeout and subsequent reset.
Watchdog Time-out Period (ms)
TD Voltage
Level
Min Nominal Max
GND 62.5 150 250
Floating 250 600 1000
V
CC
500 1200 2000
Figure 4. CAT1832 Application Circuit:
Pushbutton Reset
Figure 5. CAT1232LP Application Circuit: Watchdog Timer
Figure 6. Timing Diagram: Pushbutton Reset
Figure 7. Timing Diagram: Strobe Input
PBRST
3.3V
1
V
CC
TD
2
ST
TOL
CAT1832
µP
3
4
RESET
GND
8
7
6
5
RESET
RESET
I/O
PBRST
5V
1
10k
V
CC
TD
2
ST
TOL
CAT1232LP
µP Decoder
3
4
RESET
GND
8
7
6
5
RESET
MREQ
Address Bus
RESET
V
IH
V
IL
V
OH
V
OL
RESET
RESET
PBRST
t
PDLY
t
PB
t
RST
RESET
RESET
ST
Valid
Strobe
Valid
Strobe
Invalid
Strobe
t
RST
t
ST
t
TD
(Min)
t
TD
(Min)
Note: ST is ignored whenever a reset is active
CAT1232LP, CAT1832
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6
P1-P3P4-P6P7-P9P10-P11

CAT1232LPW-T2

Mfr. #:
Buy CAT1232LPW-T2
Manufacturer:
ON Semiconductor
Description:
Supervisory Circuits SUP 5 V
Lifecycle:
New from this manufacturer.
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