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MC100LVEL59DWG

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 4
1 Publication Order Number:
MC100LVEL59/D
MC100LVEL59
3.3VECL Triple 2:1
Multiplexer
Description
The MC100LVEL59 is a 3.3 V triple 2:1 multiplexer with
differential outputs. The output data of the multiplexers can be
controlled individually via the select inputs or as a group via the
common select input. The flexible selection scheme makes the device
useful for both data path and random logic applications.
Features
• Individual or Common Select Controls
• 500 ps Typical Propagation Delays
• ESD Protection: >2 kV HBM
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −3.8 V
• Internal Input Pulldown Resistors
• Q Output will Default LOW with Inputs Open or at V
EE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity;
Pb Pkg Level 1
Pb−Free Pkg Level 3
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−O @ 0.125 in,
Oxygen Index 28 to 34
• Transistor Count = 182 devices
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
*For additional marking information, refer to
Application Note AND8002/D.
MARKING DIAGRAM*
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G= Pb−Free Package
SO−20 WB
DW SUFFIX
CASE 751D
20
1
100LVEL59
AWLYYWWG
MC100LVEL59
http://onsemi.com
2
D1a
Figure 1. Logic Diagram and Pinout: 20−Lead SOIC (Top View)
SEL0 SEL1 D2a
1718 16 15 14 13 12
43 56789
Q0
11
10
V
CC
Q1 Q1 V
CC
Q2 Q2 V
EE
D0a
1920
21
V
CC
Q0
D0b D1bCOM_SEL D2b SEL2
10 10 10
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
Table 1. PIN DESCRIPTION
Function
ECL Input Data a
ECL Input Data b
ECL Individual Select Input
ECL Common Select Input
ECL Differential Outputs
Positive Supply
Negative Supply
Pins
D0a−D2a
D0b−D2b
SEL0−SEL2
COM_SEL
Q0−Q2; Q0−Q2
V
CC
V
EE
SEL
H
L
Table 2. TRUTH TABLE
Data
a
b
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 8 to 0 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −8 to 0 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
V
CC
V
I
V
EE
6 to 0
−6 to 0
V
V
I
out
Output Current Continuous
Surge
50
100
mA
mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction to Ambient) 0 lfpm
500 lfpm
20 SOIC
20 SOIC
140
100
°C/W
°C/W
q
JC
Thermal Resistance (Junction to Case) Standard Board 20 SOIC 30 to 35 °C/W
T
sol
Wave Solder <2 to 3 sec @ 248°C 265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
MC100LVEL59
http://onsemi.com
3
Table 4. LVPECL DC CHARACTERISTICS V
CC
= 3.3 V; V
EE
= 0.0 V (Note 1)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 27 32 27 32 27 32 mA
V
OH
Output HIGH Voltage (Note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV
V
OL
Output LOW Voltage (Note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV
V
IH
Input HIGH Voltage 2135 2420 2135 2420 2135 2420 mV
V
IL
Input LOW Voltage 1490 1825 1490 1825 1490 1825 mV
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to V
CC
− 2.0 V.
Table 5. LVNECL DC CHARACTERISTICS V
CC
= 0.0 V; V
EE
= −3.3 V (Note 3)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 27 32 27 32 27 32 mA
V
OH
Output HIGH Voltage (Note 4) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV
V
OL
Output LOW Voltage (Note 4) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV
V
IH
Input HIGH Voltage −1165 −880 −1165 −880 −1165 −880 mV
V
IL
Input LOW Voltage −1810 −1475 −1810 −1475 −1810 −1475 mV
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
4. Outputs are terminated through a 50 W resistor to V
CC
− 2.0 V.
P1-P3P4-P6

MC100LVEL59DWG

Mfr. #:
Buy MC100LVEL59DWG
Manufacturer:
ON Semiconductor
Description:
Encoders, Decoders, Multiplexers & Demultiplexers 3.3V ECL Triple 2:1 Mux
Lifecycle:
New from this manufacturer.
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