MC100LVEL59DWR2G

MC100LVEL59
http://onsemi.com
4
Table 6. AC CHARACTERISTICS V
CC
= 3.3 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
= 3.3 V (Note 5)
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
f
max
Maximum Toggle Frequency
TBD
TBD TBD
GHz
t
PLH
t
PHL
Propagation DATA to Q/Q
Delay SEL to Q/Q
COM_SEL to Q/Q
340
340
340
690
690
690
340
340
340
690
690
690
340
340
340
690
690
690
ps
t
skew
OutputOutput Skew
Any D
n
, D
m
to Q 100 100 100
ps
t
JITTER
CycletoCycle Jitter
TBD
TBD TBD
ps
t
r
t
f
Output Rise/Fall Times Q
(20% 80%)
200 540 200 540 200 540 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. V
EE
can vary ±0.3 V.
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50 W
Z
o
= 50 W
50 W 50 W
V
TT
V
TT
= V
CC
2.0 V
MC100LVEL59
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5
ORDERING INFORMATION
Device Package Package
MC100LVEL59DW SOIC20 38 Units / Rail
MC100LVEL59DWG SOIC20
(PbFree)
38 Units / Rail
MC100LVEL59DWR2 SOIC20 1000 / Tape & Reel
MC100LVEL59DWR2G SOIC20
(PbFree)
1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D ECLinPS I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
MC100LVEL59
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6
PACKAGE DIMENSIONS
20
1
11
10
B20X
H10X
C
L
18X
A1
A
SEATING
PLANE
q
h X 45
_
E
D
M
0.25
M
B
M
0.25
S
A
S
B
T
e
T
B
A
DIM MIN MAX
MILLIMETERS
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90
q 0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
__
SO20 WB
DW SUFFIX
CASE 751D05
ISSUE G
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MC100LVEL59/D
ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
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MC100LVEL59DWR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Encoders, Decoders, Multiplexers & Demultiplexers 3.3V ECL Triple 2:1 Mux
Lifecycle:
New from this manufacturer.
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