LT1512
7
1512fc
For more information www.linear.com/LT1512
operaTion
The LT1512 is a current mode switcher. This means that
switch duty cycle is directly controlled by switch current
rather than by output voltage or current. Referring to the
Block Diagram, the switch is turned “on” at the start of
each oscillator cycle. It is turned “off” when switch current
reaches a predetermined level. Control of output voltage and
current is obtained by using the output of a dual feedback
voltage sensing error amplifier to set switch current trip
level. This technique has the advantage of simplified loop
frequency compensation. A low dropout internal regula
-
tor provides a 2.3V supply for all internal circuitry on the
LT1512. This low dropout design allows input voltage to
var
y from 2.7V to 25V. A 500kHz oscillator is the basic
clock for all internal timing. It turns “on” the output switch
via the logic and driver circuitry. Special adaptive antisat
circuitry detects onset of saturation in the power switch
and adjusts driver current instantaneously to limit switch
saturation. This minimizes driver dissipation and provides
very rapid turn-off of the switch.
A unique error amplifier design has two inverting inputs
which allow for sensing both output voltage and current.
A 1.245V bandgap reference biases the noninverting input.
The first inverting input of the error amplifier is brought out
for positive output voltage sensing. The second inverting
input is driven by a “current” amplifier which is sensing
output current via an external current sense resistor. The
current amplifier is set to a fixed gain of –12.5 which
provides a –100mV current limit sense voltage.
The error signal developed at the amplifier output is brought
out externally and is used for frequency compensation.
During normal regulator operation this pin sits at a voltage
between 1V (low output current) and 1.9V (high output
current). Switch duty cycle goes to zero if the V
C
pin is
pulled below the V
C
pin threshold, placing the LT1512 in
an idle mode.
The LT1512 is an IC battery charger chip specifically op-
timized to use the SEPIC converter topology. The SEPIC
topology has unique advantages for batter
y charging. It
will operate with input voltages above, equal to or below
the batter
y voltage, has no path for battery discharge when
turned off and eliminates the snubber losses of flyback
designs. It also has a current sense point that is ground
referred and need not be connected directly to the battery.
The two inductors shown are actually just two identical
windings on one inductor core, although two separate
inductors can be used.
A current sense voltage is generated with respect to ground
across R3 in Figure 1. The average current through R3 is
always identical to the current delivered to the battery. The
LT1512 current limit loop will servo the voltage across R3
to –100mV when the battery voltage is below the voltage
limit set by the output divider R1/R2. Constant current
charging is therefore set at 100mV/R3. R4 and C4 filter
the current signal to deliver a smooth feedback voltage to
the I
FB
pin. R1 and R2 form a divider for battery voltage
sensing and set the battery float voltage. The suggested
value for R2 is 12.4k. R1 is calculated from:
applicaTions inForMaTion
R
RV
A
BAT
1
245
1 245 203
=
+
(–
V
BAT
= battery float voltage
0.3µA = typical FB pin bias current
A value of 12.4k for R2 sets divider current at 100µA.
This is a constant drain on the battery when power to the
charger is off. If this drain is too high, R2 can be increased
to 41.2k, reducing divider current to 30µA. This introduces
an additional uncorrectable error to the constant voltage
float mode of about ±0.5% as calculated by:
VError=
0.15 A(R1)(R2)
1.245(R1+R2)
BAT
± µ
±0.15µA = expected variation in FB bias current around
the nominal 0.3µA typical value.
With R2 = 41.2k and R1 = 228k, (V
BAT
= 8.2V), the error
due to variations in bias current would be ±0.42%.
A second option is to disconnect the voltage divider with
a small NMOS transistor as shown in Figure 3. To ensure
