ComLink™ Series
CY2DL814
Document #: 38-07057 Rev. *B Page 4 of 8
Table 8. D.C Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input
Parameter Description Conditions Min. Typ. Max. Unit
V
IH
Input High Voltage Guaranteed Logic High Level 2 V
V
IL
Input Low Voltage Guaranteed Logic Low Level 0.8 V
I
IH
Input High Current V
DD
= Max. V
IN
= 2.7V 1 µA
I
IL
Input Low Current V
DD
= Max. V
IN
= 0.5V –1 µA
I
I
Input High Current V
DD
= Max., V
IN
= V
DD
(Max.) 20 µA
V
IK
Clamp Diode Voltage V
DD
= Min., IIN = –18 mA –0.7 –1.2 V
V
H
Input Hysteresis 80 mV
Table 9. D.C Electrical Characteristics: 3.3V–LVDS OUTPUT
Parameter Description Conditions Min. Typ. Max. Unit
I V
OD
I Differential output voltage p-p V
DD
= 3.3V, V
IN
= V
IH
, or V
IL
RL = 100 ohm 0.25 – 0.45 V
VOC(SS) Steady-state common-mode
output voltage
––226mV
Delta
VOC(SS)
Change in VOC(SS) between
logic states
–50 3 50 mV
VOC(PP) Peak to peak common mode
output voltage
––150mV
I
OS
Output short circuit QA = 0V or QB = 0V – – –20 mA
Voh Output voltage high RL = 100 ohm – – 1475 mV
Vol Output voltage low 925 – – mV
Table 10.AC Parameters
Parameter Description Conditions Min. Typ. Max. Unit
Rise Time Pin control (pin 3) logic is “FALSE”
defaulting to 100 ohm output drivers.
Differential 20% to 80%
CL–10 pF
RL and CL to G
ND
3 CL = C
intrinsic
and C
external
RL = 100 ohm – – 1.4 ns
Fall Time ––1.4ns
Rise Time Pin control (pin 3) logic is “True”
defaulting to 50 ohm output drivers.
Differential 20% to 80%
CL–10 pF
RL and CL to G
ND
3 CL = C
intrinsic
and C
external
RL = 50 ohm
Output boost
– 350 600 ps
Fall Time – 350 600 ps
Table 11.AC Switching Characteristics @ 3.3 V (V
DD
= 3.3V ±5%, Temperature = –40°C to +85°C)
Parameter Description Conditions Min. Typ. Max. Unit
IN [+,-] to Q[A,B] Data and Clock Speed
t
PLH
Propagation Delay – Low to High V
OD
= 100 mV 3 4 5 ns
t
PHL
Propagation Delay – High to Low 3 4 5 ns
T
pd
Propagation Delay 3 4 5 ns
IN [1,2] to Q[A,B] Control Speed
T
Pe
Enable (EN) to functional operation – – 6 ns
T
pd
Functional operation to Disable – – 5 ns
Q[A,B] Output Skews
t
SK(0)
Output Skew: Skew between outputs of the same
package (in phase)
– 0.085 0.2 ns
t
SK(p)
Pulse Skew: Skew between opposite transitions of the
same output (t
PHL
–t
PLH
)
–0.2– ns
t
SK(t)
Package Skew: Skew between outputs of different
packages at the same power supply voltage, temper-
ature and package type. Same input signal level and
output load.
V
ID
= 100 mV – – 1 ns
