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IS61WV204816BLL-10TLI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
IS61/64WV204816ALL
IS61/64WV204816BLL
Integrated Silicon Solution, Inc.- www.issi.com 10
Rev. 0B
06/22/2016
WRITE CYCLE AC CHARACTERISTICS
Parameter
Symbol
-10
(1)
-12
(1)
unit
notes
Min
Max
Min
Max
Write Cycle Time
tWC
10
-
12
-
ns
CS# to Write End
tSCS
8
-
9
-
ns
Address Setup Time to Write End
tAW
8
-
9
-
ns
UB#,LB# to Write End
tPWB
8
-
9
-
ns
Address Hold from Write End
tHA
0
-
0
-
ns
Address Setup Time
tSA
0
-
0
-
ns
WE# Pulse Width
tPWE1
8
-
9
-
ns
WE# Pulse Width (OE# = LOW)
tPWE2
10
-
12
-
ns
2
Data Setup to Write End
tSD
6
-
7
-
ns
Data Hold from Write End
tHD
0
-
0
-
ns
WE# LOW to High-Z Output
tHZWE
-
4
-
5
ns
WE# HIGH to Low-Z Output
tLZWE
2
-
2
-
ns
Notes:
1 The internal write time is defined by the overlap of CS# = LOW, UB# or LB# = LOW, and WE# = LOW. All conditions must be in valid states
to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
2 Tested tPWE > tHZWE + tSD when OE# is LOW.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS# CONTROLLED, OE# = HIGH OR LOW)
ADDRESS
CS#
WE#
UB#,LB#
DOUT
DIN
tWC
tHA
tAW
tPWE
tPWB
tSA
tHZWE
tLZWE
tSD
tHD
DATA IN VALID
DATA UNDEFINED
HIGH-Z
DATA UNDEFINED
tSCS
(1)
(2)
Note:
1. tHZWE is is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before
Write Cycle.
IS61/64WV204816ALL
IS61/64WV204816BLL
Integrated Silicon Solution, Inc.- www.issi.com 11
Rev. 0B
06/22/2016
WRITE CYCLE NO. 2
(1,2)
(WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE)
ADDRESS
CS#
WE#
UB#,LB#
DOUT
DIN
tWC
tHA
tAW
tPWE
tPWB
tSA
tHZOE
tSD
tHD
DATA IN VALID
DATA UNDEFINED
HIGH-Z
DATA UNDEFINED
tSCS
(1)
(2)
OE#
Notes:
1. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
WRITE CYCLE NO. 3
(1)
(WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE)
tWC
tHA
tAW
tPWE2
tSA
tHZWE tLZWE
HIGHZ
tSD tHD
DATA UNDEFINED
DATA IN VALID
ADDRESS
CS#=LOW
WE#
DOUT
DIN
OE# = LOW
tPWB
UB#,LB#
Note:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
IS61/64WV204816ALL
IS61/64WV204816BLL
Integrated Silicon Solution, Inc.- www.issi.com 12
Rev. 0B
06/22/2016
WRITE CYCLE NO. 4
(1, 2, 3)
(UB# & LB# Controlled, CS# = OE# = LOW)
ADDRESS
WE#
DOUT
DIN
tSA
tHZWE
tPWB
tHA
DATA IN
VALID
ADDRESS 1
ADDRESS 2
tWC
DATA IN
VALID
DATA UNDEFINED
tHD
tSD
HIGH-Z
tLZWE
WORD 1
WORD 2
UB#, LB#
tHA
OE#=LOW
CS#=LOW
tSA
tPWB
tWC
Notes:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
2. Due to the restriction of note1, OE# is recommended to be HIGH during write period.
3. WE# stays LOW in this example. If WE# toggles,, tPWE and tHZWE must be considered.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

IS61WV204816BLL-10TLI

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Description:
SRAM 32Mb High-Speed Async 1Mbx16 10ns
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