© 2000 Fairchild Semiconductor Corporation DS010964 www.fairchildsemi.com
October 1991
Revised May 2000
SCAN18540T Inverting Line Driver with 3-STATE Outputs
SCAN18540T
Inverting Line Driver with 3-STATE Outputs
General Description
The SCAN18540T is a high speed, low-power line driver
featuring separate data inputs organized into dual 9-bit
bytes with byte-oriented paired output enable control sig-
nals. This device is compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture with the
incorporation of the defined boundary-scan test logic and
test access port consisting of Test Data Input (TDI), Test
Data Out (TDO), Test Mode Select (TMS), and Test Clock
(TCK).
Features
■ IEEE 1149.1 (JTAG) compliant
■ Dual output enable signals per byte
■ 3-STATE outputs for bus-oriented applications
■ 9-bit data busses for parity applications
■ Reduced-swing outputs source 32 mA/sink 64 mA
■ Guaranteed to drive 50
Ω transmission line to TTL input
levels of 0.8V and 2.0V
■ TTL compatible inputs
■ 25 mil pitch SSOP (Shrink Small Outline Package)
■ Includes CLAMP and HIGHZ instructions
■ Member of Fairchild’s SCAN products
Ordering Code:
Connection Diagram Pin Descriptions
Truth Tables
H = HIGH Voltage Level X = Immaterial
L = LOW Voltage Level Z = High Impedance
Order Number Package Number Package Description
SCAN18540TSSC MS54A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Pin Names Description
AI
(0–8)
Input pins, A side
BI
(0–8)
Input pins, B side
AOE
1
, AOE
2
3-STATE Output Enable Input pins, A side
BOE
1
, BOE
2
3-STATE Output Enable Input pins, B side
AO
(0–8)
Output pins, A side
BO
(0–8)
Output pins, B side
Inputs
AO
(0–8)
AOE
1
AOE
2
AI
(0–8)
LL H L
HX X Z
XH X Z
LL L H
Inputs
BO
(0–8)
BOE
1
BOE
2
BI
(0–8)
LL H L
HX X Z
XH X Z
LL L H
