2
ICS95V842
0830B—11/24/08
Pin Descriptions
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
"True" reference clock input.
"Complementary" reference clock input.
3.3V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
9 FB_OUTC OUT
Complement single-ended feedback output, dedicated external
feedback. It switches at the same frequency as other DDR outputs,
This output must be connect to FB_INC.
10 FB_OUTT OUT
True single-ended feedback output, dedicated external feedback. It
switches at the same frequency as other DDR outputs, This output
must be connect to FB_INT.
11 FB_INT IN
True single-ended feedback input, provides feedback signal to interna
PLL for synchronization with CLK_INT to eliminate phase error.
12 FB_INC IN
Complement single-ended feedback input, provides feedback signal to
internal PLL for synchronization with CLK_INT to eliminate phase
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
16 GND PWR Ground pin.