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95V842AFILFT

P1-P3P4-P6P7-P9
4
ICS95V842
0830B—11/24/08
Timing Requirements
T
A
= 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN MAX UNITS
Max clock frequency
3
freq
op
33 233 MHz
Application Frequency
Range
3
freq
App
60 220 MHz
Input clock duty cycle d
tin
40 60 %
CLK stabilization T
STAB
100 µs
DC Electrical Characteristics
TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V
DDQ
, A
VDD
2.3 2.5 2.7 V
Low level input voltage V
IL
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.4 V
DD
/2 - 0.18 V
High level input voltage V
IH
CLK_INT, CLK_INC, FB_INC,
FB_INT
V
DD
/2 + 0.18 2.1 V
DC input signal voltage
(note 1,2)
V
IN
-0.3 V
DD
+ 0.3 V
Differential input signal
voltage (note 3)
V
ID
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.36 V
DD
+ 0.6 V
Differential output voltage
(note 3)
V
OD
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.7 V
DD
+ 0.6 V
Output differential cross-
voltage (note 4)
V
OX
V
DD
/2 - 0.15 V
DD
/2 + 0.15 V
Input differential cross-
voltage (note 4)
V
IX
V
DD
/2 - 0.2 V
DD
/2 V
DD
/2 + 0.2 V
Operating free-air
temperature
T
A
085°C
Notes:
1
2
3
4
Differential input signal voltage specifies the differential voltage [VTR-VCP] required for switching,
where VTR is the true input level and VCP is the complementary input level.
Differential cross-point voltage is expected to track variations of VDD and is the voltage at which
the differential signal must be crossing.
Unused inputs must be held high or low to prevent them from floating.
DC input signal voltage specifies the allowable DC excursion of differential input.
5
ICS95V842
0830B—11/24/08
Notes:
1.
2.
3.
4. Does not include jitter.
Switching characteristics are guaranteed for application frequency range. The
PLL Locks over the Max Clock Frequency range, but the device doe not
necessarily meet other timing parameters.
Refers to transition on noninverting output in PLL bypass mode.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,
were the cycle (tc) decreases as the frequency goes up.
Switching Characteristics
T
A
= 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Max clock frequency
3
freq
op
40 333 MHz
Application Frequency
Range
3
freq
App
60 220 MHz
Input clock duty cycle
d
tin
40 60 %
Input clock slew rate
t
sl(I)
12v/ns
CLK stabilization
T
STAB
100 µs
Low-to high level propagation
delay time
t
PLH
1
CLK_IN to any output 5.5 ns
High-to low level propagation
delay time
t
PHL
1
CLK_IN to any output 5.5 ns
Output enable time
t
en
PD# to any output 5 ns
Output disable time
t
dis
PD# to any output 5 ns
Period jitter
t
jit (per)
-75 75 ps
Half-period jitter
t
jit(hper)
-75 75 ps
Output clock slew rate
t
sl(o)
12.5v/ns
Cycle to Cycle Jitter
t
cyc
-t
cyc
-75 75 ps
Static Phase Offset
t
(spo)
-50 50 ps
Output to Output Skew
t
skew
40 60 ps
Over the application
frequency range
6
ICS95V842
0830B—11/24/08
GND
ICS95V842
V
DD
V
DD
/2
V
(CLKC)
V
(CLKC)
SCOPE
C=14pF
-V
DD/2
-V
DD/2
-V
DD/2
V
DD/2
Z=60Ω
Z=60Ω
Z=50Ω
Z=50Ω
R=10Ω
R=10Ω
R=50Ω
R=60Ω
R=60Ω
R=50Ω
V
(TT)
V
(TT)
C=14pF
NOTE: V
(TT)
=
GND
t
c(n)
t
c(n+1)
t
jit(cc)
=t
c(n)
±t
c(n+1)
Figure 1. IBIS Model Output Load
Figure 2. Output Load Test Circuit
Y , FB_OUTC
X
Y , FB_OUTT
X
Parameter Measurement Information
ICS95V842
Figure 3. Cycle-to-Cycle Jitter
P1-P3P4-P6P7-P9

95V842AFILFT

Mfr. #:
Buy 95V842AFILFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2.5V PHASE LOCK LOOP
Lifecycle:
New from this manufacturer.
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