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7016L12PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
10
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. t
WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t
DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = V
IL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing
(1,5)
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE or SEM
(6)
(4) (4)
(3)
3190 drw 09
(7)
(9)
(7)
t
LZ
3190 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
CE or SEM
R/W
t
AW
t
EW
(3)
(2)
(6)
(9)
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
11
Timing Waveform of Semaphore Read after Write Timing, Either
Side
(1)
NOTES:
1. D
OR = DOL =VIH, CER = CEL =VIH.
2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W
“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If t
SPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
Timing Waveform of Semaphore Write Condition
(1,3,4)
NOTES:
1. CE = V
IH for the duration of the above timing (both write and read cycle).
2. “DATA
OUT VALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value.
SEM
3190 drw 11
t
AW
t
SOP
I/O
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID
DATA
OUT
t
DW
t
DH
t
AS
t
AOE
Read Cycle
Write Cycle
A
0
-A
2
OE
VALID
(2)
t
SWRD
t
EW
t
WP
SEM
"A"
3190 drw 12
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
SIDE
"B"
(2)
A
0"B"
-A
2"B"
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and BUSY (M/S = V
IH)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".
6. 'X' in part numbers indicates power rating (S or L).
7016X12
Com'l Only
7016X15
Com'l Only
Symbol Parameter Min. Max. Min. Max. Unit
BUSY TIMING (M/S = V
IH
)
t
BAA
BUSY Access Time from Address Match
____
12
____
15 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
12
____
15 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
12
____
15 ns
t
BDC
BUSY Disable Time from Chip Enable High
____
12
____
15 ns
t
APS
Arbitration Priority Set-up Time
(2 )
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3 )
____
15
____
18 ns
t
WH
Write Hold After BUSY
(5 )
11
____
13
____
ns
BUSY INPUT TIMING (M/S = V
IL
)
t
WB
BUSY Input to Write
(4 )
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5 )
11
____
13
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1 )
____
25
____
30 ns
t
DD D
Write Data Valid to Read Data Delay
(1)
____
20
____
25 ns
3190 tbl 14a
7016X20
Com'l, Ind
& Military
7016X25
Com'l &
Military
7016X35
Com'l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (M/S = V
IH
)
t
BAA
BUSY Access Time from Address Match
____
20
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
20
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
20
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable High
____
17
____
17
____
20 ns
t
APS
Arbitration Priority Set-up Time
(2 )
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3 )
____
30
____
30
____
35 ns
t
WH
Write Hold After BUSY
(5 )
15
____
17
____
25
____
ns
BUSY INPUT TIMING (M/S = V
IL
)
t
WB
BUSY Input to Write
(4 )
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5 )
15
____
17
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1 )
____
45
____
50
____
60 ns
t
DD D
Write Data Valid to Read Data Delay
(1)
____
30
____
35
____
45 ns
3190 tbl 14b
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

7016L12PF

Mfr. #:
Buy 7016L12PF
Manufacturer:
IDT
Description:
SRAM 8KX8 DUAL PORT BUSY/INT
Lifecycle:
New from this manufacturer.
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