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MC74HCT374ADW

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 12
1 Publication Order Number:
MC74HCT374A/D
MC74HCT374A
Octal 3-State Noninverting
D Flip-Flop with
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT374A may be used as a level converter for
interfacing TTL or NMOS outputs to High−Speed CMOS inputs.
The HCT374A is identical in pinout to the LS374.
Data meeting the setup and hold time is clocked to the outputs with
the rising edge of Clock. The Output Enable does not affect the state of
the flip−flops, but when Output Enable is high, the outputs are forced
to the high−impedance state. Thus, data may be stored even when the
outputs are not enabled.
The HCT374A is identical in function to the HCT574A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT534A, which has
inverting outputs.
Features
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS−Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 mA
• In Compliance With the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 276 FETs or 69 Equivalent Gates
• Improvements over HCT374
♦ Improved Propagation Delays
♦ 50% Lower Quiescent Power
♦ Improved Input Noise and Latchup Immunity
• These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
DATA
INPUTS
D0
11
CLOCK
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
8
7
4
3
1
OUTPUT ENABLE
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
16
15
12
9
6
5
2
PIN 20 = V
CC
PIN 10 = GND
NONINVERTING
OUTPUTS
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MARKING DIAGRAMS
HCT
374A
ALYWG
G
See detailed ordering and shipping information on page 5 o
f
this data sheet.
ORDERING INFORMATION
20
1
HCT374A
AWLYYWWG
20
1
SOIC−20
TSSOP−20
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
Q2
D1
D0
Q0
OUTPUT ENABLE
GND
Q3
D3
D2
Q1
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q6
D6
D7
Q7
V
CC
CLOCK
Q4
D4
D5
Q5
FUNCTION TABLE
Inputs Output
Output
Enable Clock D Q
LHH
LLL
L L,H, X No Change
HXXZ
X = don’t care
Z = high impedance
MC74HCT374A
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2
Design Criteria Value Units
Internal Gate Count* 69 ea.
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0
mW
Speed Power Product .0075 pJ
*Equivalent to a two−input NAND gate.
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±35 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±75 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature –65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types –55 +125
_C
t
r
, t
f
Input Rise and Fall Time (Figure 1) 0 500 ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HCT374A
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3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbo
l
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
−55 to
25_C
≤ 85_C ≤ 125_C
V
IH
Minimum High−Level Input Voltage V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| ≤ 20 mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low−Level Input Voltage V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| ≤ 20 mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
OH
Minimum High−Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
| ≤ 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
V
in
= V
IH
or V
IL
|I
out
| ≤ 6.0 mA 4.5 3.98 3.84 3.7
V
OL
Maximum Low−Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
| ≤ 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| ≤ 6.0 mA 4.5 0.26 0.33 0.4
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 5.5 ±0.1 ±1.0 ±1.0
mA
I
OZ
Maximum Three−State Leakage
Current
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
5.5 ±0.5 ±5.0 ±10
mA
I
CC
Maximum Quiescent Supply Current
(per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
5.5 4.0 40 160
mA
DI
CC
Additional Quiescent Supply Current V
in
= 2.4 V, Any One Input
V
in
= V
CC
or GND, Other Inputs
l
out
= 0 mA
5.5
≥ −55_C 25_C to 125_C
mA
2.9 2.4
1. Total Supply Current = I
CC
+ ΣDI
CC
.
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ±10%, C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbo
l
Parameter
Guaranteed Limit
Unit
−55 to 25_C ≤ 85_C ≤ 125_C
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
30 24 20 MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
31 39 47 ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
30 38 45 ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
30 38 45 ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
12 15 18 ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
out
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
15 15 15 pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Flip−Flop)* 65 pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
P1-P3P4-P6P7-P7

MC74HCT374ADW

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Buy MC74HCT374ADW
Manufacturer:
ON Semiconductor
Description:
IC FF D-TYPE SNGL 8BIT 20SOIC
Lifecycle:
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