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NB3N2304NZDTG

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 6
1 Publication Order Number:
NB3N2304NZ/D
NB3N2304NZ
3.3V 1:4 Clock Fanout
Buffer
Description
The NB3N2304NZ is a low skew 1−to 4 clock fanout buffer,
designed for high speed clock distribution such as in PCI−X
applications. The NB3N2304NZ guarantees low output−to−output
skew. Optimal design, layout and processing minimizes skew within a
device and from device−to−device.
The Output Enable (OE) pin forces the outputs LOW when LOW.
Features
• Input/Output Clock Frequency up to 140 MHz
• Low Skew Outputs (100 ps)
• Output Enable
• Operating Range: V
DD
= 3.0 V to 3.6 V
• Ideal for PCI−X and networking clocks
• Packaged in 8−pin TSSOP, 4.4 mm x 3 mm
• Industrial Temperature Range
• These are Pb−Free Devices*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
TSSOP−8
DT SUFFIX
CASE 948S
MARKING
DIAGRAM*
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
Figure 1. Simplified Logic Diagram
40N
YWW
AG
A = Assembly Location
Y = Year
WW = Work Week
M
= Date Code
G = Pb−Free Package
DFN8
MN SUFFIX
CASE 506AA
6O M
14
1
NB3N2304NZ
http://onsemi.com
2
Figure 2. Block Diagram
Figure 3. NB3N2304NZ Package Pinout (Top View)
Q1
Q2
Q3
Q4
IN
Logic
Control
OE
1
2
3
4
8
7
6
5
Q4
Q3
V
DD
Q2
IN
OE
Q1
GND
Table 1. PIN DESCRIPTION
Pin #
Pin
Name
Type Description
1 IN LVCMOS/LVTTL Input Clock Input
2 OE LVCMOS/LVTTL Input Output Enable for the clock outputs. Outputs are enabled when forced HIGH. Outputs
are forced to logic LOW when OE is forced LOW.
3 Q1 LVCMOS/LVTTL Output Clock Output 1
4 GND Power Negative Supply Voltage; Connect to Ground, 0 V
5 Q2 (LV)CMOS/(LV)TTL Input Clock Output 2
6 V
DD
Power Positive Supply Voltage (3.0 V to 3.6 V)
7 Q3 (LV)CMOS/(LV)TTL Output Clock Output 3
8 Q4 (LV)CMOS/(LV)TTL Input Clock Output 4
− EP Thermal Exposed Pad (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit.
Electrically connect to the most negative supply (GND) or leave unconnected, floating
open.
Table 2. OE, OUTPUT ENABLE FUNCTION TABLE
Inputs Outputs
IN OE
L L L
H L L
L H L
H H H
NB3N2304NZ
http://onsemi.com
3
Table 3. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
> 2kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
TSSOP−8
DFN−8
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−O @ 0.125 in
Transistor Count 480 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
DD
Positive Power Supply GND = 0 V V
DD
+ 0.5V V
V
I
Input Voltage GND – 0.5 v
V
I
v V
DD
+ 0.5
V
T
A
Operating Temperature Range, Industrial w −40 to v +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
DFN−8
DFN−8
143
103
129
84
°C/W
T
SOL
Wave Solder Pb−Free (Note 2) 265 °C
q
JC
Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
P1-P3P4-P6P7-P7

NB3N2304NZDTG

Mfr. #:
Buy NB3N2304NZDTG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer LOW SKEW 1:4 CLK
Lifecycle:
New from this manufacturer.
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