ICS8530FY-01 REVISION G NOVEMBER 15, 2012 4 ©2012 Integrated Device Technology, Inc.
ICS8530-01 Data Sheet LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Table 4B. Differential Input DC Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 4C. LVPECL DC Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
NOTE 1: Outputs terminated with 50 to V
CCO
– 2V.
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
CLK V
IN
= V
CC
= 3.465V 150 µA
nCLK V
IN
= V
CC
= 3.465V 5 µA
I
IL
Input Low Current
CLK V
IN
= 0V, V
CC
= 3.465V -5 µA
nCLK V
IN
= 0V, V
CC
= 3.465V -150 µA
V
PP
Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V
V
CMR
Common Mode Input Voltage; NOTE 1, 2 V
EE
+ 0.5 V
CC
– 0.85 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 V
CCO
– 1.4 V
CCO
– 0.9 V
V
OL
Output Low Voltage; NOTE 1 V
CCO
– 2.0 V
CCO
– 1.7 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.6 1.0 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency
500 MHz
t
JIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
106.25MHz,
Integration Range: 12kHz – 20MHz
0.03 ps
t
PD
Propagation Delay; NOTE 1 ƒ 500MHz 1 2 ns
tsk(o) Output Skew; NOTE 2, 3 75 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 148 305 ps
t
R
/ t
F
Output Rise/ Fall Time 20% to 80% @ 50MHz 300 750 ps
odc Output Duty Cycle 47 50 53 %
ICS8530FY-01 REVISION G NOVEMBER 15, 2012 5 ©2012 Integrated Device Technology, Inc.
ICS8530-01 Data Sheet LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Additive Phase Jitter @ 106.25MHz
12kHz to 20MHz = 0.03ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
ICS8530FY-01 REVISION G NOVEMBER 15, 2012 6 ©2012 Integrated Device Technology, Inc.
ICS8530-01 Data Sheet LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Parameter Measurement Information
3.3V Output Load AC Test Circuit
Output Skew
Output Duty Cycle/Pulse Width/Period
Differential Input Level
Part-to-Part Skew
Propagation Delay
SCOPE
Qx
nQx
V
EE
-1.3V±0.165V
V
CC,
V
CCO
2V
nQx
Qx
nQy
Qy
tsk(o)
Q[0:15]
nQ[0:15]
nCLK
CLK
V
CC
V
EE
V
CMR
Cross Points
V
PP
tsk(pp)
P
art 1
P
art 2
nQx
Qy
Qx
nQy
t
PD
Q[0:15]
nQ[0:15]
CLK
nCLK

8530FY-01LF

Mfr. #:
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IDT
Description:
Clock Drivers & Distribution FANOUT BUFFER
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