NTS0102 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 23 January 2013 16 of 27
NXP Semiconductors
NTS0102
Dual supply translating transceiver; open drain; auto direction sensing
The gate bias voltage of the pass gate transistor (T3) is set at approximately one
threshold voltage above the V
CC
level of the low-voltage side. During a LOW-to-HIGH
transition the output one-shot accelerates the output transition by switching on the PMOS
transistors (T1, T2) bypassing the 10 k pull-up resistors and increasing current drive
capability. The one-shot is activated once the input transition reaches approximately
V
CCI
/2; it is de-activated approximately 50 ns after the output reaches V
CCO
/2. During the
acceleration time the driver output resistance is between approximately 50 and 70 . To
avoid signal contention and minimize dynamic I
CC
, the user should wait for the one-shot
circuit to turn-off before applying a signal in the opposite direction. Pull-up resistors are
included in the device for DC current sourcing capability.
14.3 Input driver requirements
As the NTS0102 is a switch type translator, properties of the input driver directly effect the
output signal. The external open-drain or push-pull driver applied to an I/O determines the
static current sinking capability of the system; the max data rate, HIGH-to-LOW output
transition time (t
THL
) and propagation delay (t
PHL
) are dependent upon the output
impedance and edge-rate of the external driver. The limits provided for these parameters
in the datasheet assume a driver with output impedance below 50 is used.
14.4 Output load considerations
The maximum lumped capacitive load that can be driven is dependant upon the one-shot
pulse duration. In cases with very heavy capacitive loading there is a risk that the output
will not reach the positive rail within the one-shot pulse duration.
To avoid excessive capacitive loading and to ensure correct triggering of the one-shot it's
recommended to use short trace lengths and low capacitance connectors on NTS0102
PCB layouts. To ensure low impedance termination and avoid output signal oscillations
and one-shot re-triggering, the length of the PCB trace should be such that the round trip
delay of any reflection is within the one-shot pulse duration (approximately 50 ns).
14.5 Power up
During operation V
CC(A)
must never be higher than V
CC(B)
, however during power-up
V
CC(A)
V
CC(B)
does not damage the device, so either power supply can be ramped up
first. There is no special power-up sequencing required. The NTS0102 includes circuitry
that disables all output ports when either V
CC(A)
or V
CC(B)
is switched off.
14.6 Enable and disable
An output enable input (OE) is used to disable the device. Setting OE = LOW
causes all I/Os to assume the high-impedance OFF-state. The disable time (t
dis
with no
external load) indicates the delay between when OE goes LOW and when outputs
actually become disabled. The enable time (t
en
) indicates the amount of time the user
must allow for one one-shot circuitry to become operational after OE is taken HIGH. To
ensure the high-impedance OFF-state during power-up or power-down, pin OE should be
tied to GND through a pull-down resistor, the minimum value of the resistor is determined
by the current-sourcing capability of the driver.
