74ACTQ16240SSC

May 1991
Revised November 1998
74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS010924.prf www.fairchildsemi.com
74ACTQ16240
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ16240 contains sixteen inverting buffers with 3-
STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is nibble controlled. Each nibble has
separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ACTQ16240 utilizes Fairchild’s Quiet Series technol-
ogy to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control for superior performance.
Features
Utilizes Fairchild’s FACT Quiet Series technology
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed pin-to-pin output skew
Separate control logic for each byte
16-bit version of the ACTQ240
Outputs source/sink 24 mA
Additional specs for multiple output switching
Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
Pin Assignment
for SSOP and TSSOP
FACT, FACT Quiet Series, Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACTQ16240SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Inputs (Active Low)
I
0
–I
15
Inputs
O
0
–O
15
Outputs
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74ACTQ16240
Truth Tables
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Z = High Impedance
Functional Description
The ACTQ16240 contains sixteen inverting buffers with 3-
STATE standard outputs. The device is nibble (4 bits) con-
trolled with each nibble functioning identically, but indepen-
dently of the other. The control pins may be shorted
together to obtain full 16-bit operation. The 3-STATE out-
puts are controlled by an Output Enable (OE
n
) input for
each nibble. When OE
n
is LOW, the outputs are in 2-state
mode. When OE
n
is HIGH, the outputs are in the high
impedance mode, but this does not interfere with entering
new data into the inputs.
Logic Diagram
Inputs Outputs
OE
1
I
0
–I
3
O
0
–O
3
LL H
LH L
HX Z
Inputs Outputs
OE
2
I
4
–I
7
O
4
–O
7
LL H
LH L
HX Z
Inputs Outputs
OE
3
I
8
–I
11
O
8
–O
11
LL H
LH L
HX Z
Inputs Outputs
OE
4
I
12
–I
15
O
12
–O
15
LL H
LH L
HX Z
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74ACTQ16240
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched HIGH and one output held HIGH.
Note 7: Maximum number of data inputs (n) switching. (n 1) input switching 0V to 3V. Input under test switching 3V to threshold (V
ILD
).
Supply Voltage (V
CC
) 0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= 0.5V 20 mA
V
I
= V
CC
+ 0.5V +20 mA
DC Output Diode Current (I
OK
)
V
O
= 0.5V 20 mA
V
O
= V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) 0.5V to V
CC
+ 0.5V
DC Output Source/Sink Current (I
O
) ± 50 mA
DC V
CC
or Ground Current
per Output Pin ± 50 mA
Junction Temperature +140°C
Storage Temperature 65°C to +150°C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (V
O
)0V to V
CC
Operating Temperature (T
A
) 40°C to +85°C
Minimum Input Edge Rate (V/t) 125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol Parameter
V
CC
T
A
= +25°C
T
A
= 40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum High 4.5 1.5 2.0 2.0 V V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or V
CC
0.1V
V
IL
Maximum Low 4.5 1.5 0.8 0.8 V V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or V
CC
0.1V
V
OH
Minimum High 4.5 4.49 4.4 4.4 V I
OUT
= 50 µA
Output Voltage 5.5 5.49 5.4 5.4
V
IN
= V
IL
or V
IH
4.5 3.86 3.76 V I
OH
= 24 mA
5.5 4.86 4.76 I
OH
= 24 mA (Note 2)
V
OL
Maximum Low 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
V
IN
= V
IL
or V
IH
4.5 0.36 0.44 V I
OL
= 24 mA
5.5 0.36 0.44 I
OL
= 24 mA (Note 2)
I
OZ
Maximum 3-STATE 5.5 ±0.5 ±5.0 µAV
I
= V
IL
, V
IH
Leakage Current V
O
= V
CC
, GND
I
IN
Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAV
I
= V
CC
, GND
I
CCT
Maximum I
CC
/Input 5.5 0.6 1.5 mA V
I
= V
CC
2.1V
I
CC
Max Quiescent Supply Current 5.5 8.0 80.0 µAV
IN
= V
CC
or GND
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 75 mA V
OHD
= 3.85V Min
V
OLP
Quiet Output 5.0 0.5 0.8 V Figure 1Figure 2
Maximum Dynamic V
OL
(Note 5)(Note 6)
V
OLV
Quiet Output Minimum Dynamic V
OL
5.0 0.5 1.0 V Figure 1Figure 2
(Note 5)(Note 6)
V
OHP
Maximum Overshoot 5.0 V
OH
+ 1.0 V
OH
+ 1.5 V Figure 1Figure 2
(Note 4)(Note 6)
V
OHV
Minimum V
CC
Droop 5.0 V
OH
1.0 V
OH
1.8 V Figure 1Figure 2
(Note 4)(Note 6)
V
IHD
Minimum High Dynamic Input Voltage Level 5.0 1.7 2.0 V (Note 4)(Note 7)
V
ILD
Maximum Low Dynamic Input Voltage Level 5.0 1.2 0.8 V (Note 4)(Note 7)

74ACTQ16240SSC

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Buffers & Line Drivers 16-Bit Buf/Line Drv
Lifecycle:
New from this manufacturer.
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