which can be achieved using power-down between
conversions.
External Compensation
Figure 19a shows the connection for external compensa-
tion with reference adjustment. In this mode, an external
4.7µF capacitor compensates the reference output
amplifier, allowing for maximum conversion speed and
lowest conversion noise. However, when reactivating the
ADC after power-down, the reference takes typically 2ms
to fully charge the 4.7µF capacitor, so more time is
required before a conversion can start (Figure 19b).
Thus, the average current consumed in power-up/power-
down operations is higher in external compensation
mode than in internal compensation mode.
Gain and Offset Adjustment
Figure 20 depicts the nominal, unipolar input/output (I/O)
transfer function, and Figure 22 shows the bipolar I/O
transfer function. Code transitions occur halfway between
successive integer LSB values. Note that 1LSB = 1.00mV
(4.096V/4096) for unipolar operation and 1LSB = 1.00mV
((4.096V/2 - -4.096V/2)/4096) for bipolar operation.
Figures 19a and 21a show how to adjust the ADC gain
in applications that require full-scale range adjustment.
The connection shown in Figure 21a provides ±0.5%
for ±20LSBs of adjustment range and is recommended
for applications that use an external reference. On the
other hand, Figure 19a is recommended for applica-
tions that use the internal reference, because it uses
fewer external components.
If both offset and full scale need adjustment, the circuit
in Figure 21b is recommended. For single-supply
ADCs, it is virtually impossible to null system negative
offset errors. However, the MAX191 input configuration
is pseudo-differential—only the difference in voltage
between AIN+ and AIN- will be converted into its digital
representation. By applying a small positive voltage to
AIN-, the 0 input voltage at AIN+ can be adjusted to
above or below AIN- voltage, thus nulling positive or
negative system offset errors. R9 and R10 can be
removed for applications that require only positive sys-
tem errors to be nulled. To trim the offset error of the
MAX191, apply 1/2LSB to the analog input and adjust
R6 so the digital output code changes between 000
(hex) and 001 (hex). To adjust full scale, apply FS - 1
1/2LSBs and adjust R2 until the output code changes
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
______________________________________________________________________________________ 19
25µs
RD
0
1
PD
20µs15µs
VREF
Figure 18b. Low Average-Power Mode Operation (Internal
Compensation)
10,000
10
10
100
1000
fg18c
CONVERSIONS PER SECOND
SUPPLY CURRENT (µA)
50 200
1k 5k 20k
100k
Figure 18c. Average Supply Current vs. Conversion Rate,
Powering Down Between Conversions
MAX191
VREF
REFADJ
PD
1
5
6
0.1µF
4.7µF
5k
11k
15k
100k
0.01µF
Figure 19a. External-Compensation Mode with Internal
Reference Adjustment Circuit
MAX191
between FFE (hex) and FFF (hex). Because interaction
occurs between adjustments, offset should be adjusted
before gain. For an input gain of two, remove R7 and R8.
The MAX191 accepts input voltages from AGND to V
DD
while operating from a single supply, and V
SS
to V
DD
when operating from dual supplies. Figure 22 shows
the bipolar input transfer function with AIN- connected
to midscale for single-supply operation and connected
to GND operating from dual supplies. When operating
from a single supply, the MAX191 can be configured
for bipolar operation on its pseudo-differential input.
Instead of using AIN- as an analog input return, AIN-
can be set to a different positive potential voltage
above ground (BIP pin is set high). The sampled ana-
log input (AIN+) can swing to any positive voltage
above and below AIN-, and the ADC performs bipolar
conversions with respect to AIN-. When operating from
dual supplies, the MAX191 full-scale range is from
-V
REF
/2 to +V
REF
/2.
Digital Bus Noise
If the data bus connected to the ADC is active during a
conversion, crosstalk from the data pins to the ADC
comparator may generate errors. Slow-memory mode
avoids this problem by placing the µP in a wait state
during the conversion. In ROM mode, if the data bus is
active during the conversion, it should be isolated from
the ADC using three-state drivers.
The ADC generates considerable digital noise in ROM
mode when RD or CS go high and the output data dri-
vers are disabled after a conversion has started. This
noise can cause large errors if it occurs when the SAR
latches a comparator decision. To avoid this problem,
RD and CS should be active for less than one clock
cycle. If this is not possible, RD or CS should go high at
the rising edge of CLK, since the comparator output is
always latched on falling edges of CLK.
Layout, Grounding, Bypassing
Use printed circuit boards for best system performance.
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
20 ______________________________________________________________________________________
RD
0
OPEN CIRCUIT (FLOAT)
PD
12.5µs
2ms
VREF
200ms
Figure 19b. Low Average-Power Mode Operation (External
Compensation)
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
0 1 2 3
FS
FS–1LSB
OUTPUT
CODE
FULL-SCALE
TRANSITION
FS = VREF
1LSB =
4096
FS
AIN INPUT VOLTAGE (LSB)
Figure 20. Unipolar Transfer Function
V
IN
R3
10k
R1
100
R2
49.9
R4
10k
TO AIN+
MAX480
Figure 21a. Trim Circuit for Gain (±0.5%)
Wire-wrap boards are not recommended. Board layout
should ensure that digital- and analog-signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 23 shows the recommended system ground
connections. Establish a single-point ground (“star”
ground point) at AGND, separate from the logic
ground. Connect all other analog grounds and DGND
to it. No other digital-system ground should be con-
nected to this single-point analog ground. The ground
return to the power supply for this star ground should
be low impedance and as short as possible for noise-
free operation.
High-frequency noise in the V
DD
power supply may
affect the high-speed comparator in the ADC. Bypass
these supplies to the single-point analog ground with
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
______________________________________________________________________________________ 21
MAX191
AIN +
AIN -
D0–D11
V
IN
R7
10k
R8
10k
VREF
R6
10k
R5
10k
R1
10k
R2
100
R3
10k
R4
49.9
VREF
R9*
20k
0.1µF*
R10*
49.9
* CONNECT AIN- TO AGND WHEN USING DUAL SUPPLIES
MAX480
Figure 21b. Offset (±10mV) and Gain (±1%) Trim Circuit
01 . . . 111
01 . . . 110
00 . . . 010
00 . . . 001
11 . . . 111
11 . . . 110
00 . . . 000
10 . . . 001
10 . . . 000
11 . . . 101
0V
VREF - 1LSB
VREF
––––
2
0V
SINGLE SUPPLY
VREF
AIN- = ––––
2
(
)
DUAL SUPPLY
AIN- = 0V
VREF
–––– - 1LSB
2
-VREF
––––
2
Figure 22. Bipolar Transfer Function
SUPPLIES
+5V
-5V
GND
V
DD
AGND V
SS
DGND
+5V DGND
R* = 10
DIGITAL
CIRCUITRY
*OPTIONAL
MAX191
Figure 23. Power-Supply Grounding Connection

MAX191BCWG

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down
Lifecycle:
New from this manufacturer.
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