4
Electrical & Optical Specifications (Ta=25°C)
Parameters Symbol Minimum Typical Maximum Units Conditions
Input
Logic High Input Voltage V
IH
0.7*V
CC
V
Logic Low Input Voltage V
IL
0.3* V
CC
V
Logic High Input Current I
IH
0.1 PAV
I
V
IH
Logic Low Input Current I
IL
0.1 PAV
I
V
IL
Shutdown Current I
SD
1 PA Vcc = 3.0 V, TRG = X, PWR = 0
Standby Current I
SB
70 100 PA Vcc = 3.0 V, TRG = 0, PWR = 1
Output
Digital Output Low Level V
OL
0 0.3 V I
DOUT(Low)
= 2 mA, Vcc = 3.0 V
Digital Output High Level V
OH
Vcc – 0.3 V Vcc = 3.0 V, R2 = 10k:
Built-in Resistor at PFILT R
FILT
100k, 300k,
500k
:
Through I
2
C set.
Transmitter
I
LED
Pulse Current I
LED
125 235 mA Vcc = 3.0 V, R1 = 10:
Number of LED Pulse 16 x (1, 2, …,
16 times)
Through I
2
C set.
LED Pulse Frequency 12.5, 25, 50,
100
kHz Through I
2
C set.
Pulse Duty Cycle = 50%.
LED Burst Duration vs.
OFF Period
1/16, 1/64,
1/128, 1/256
Through I
2
C set.
Receiver
Photodiode Input
Current (PD)
I
PD
03PA
Current Gain I
PFILT
/I
PD
20 times Vcc = 3.0 V
[1]
Comparator Threshold
Threshold voltage V
TH
0.12
0.17
0.22
0.27
0.32
0.37
0.42
0.47
0.52
0.57
0.62
0.67
0.72
0.77
0.82
0.87
V TH = 0000,
TH = 0001,
TH = 0010,
TH = 0011,
TH = 0100,
TH = 0101,
TH = 0110,
TH = 0111,
TH = 1000,
TH = 1001,
TH = 1010,
TH = 1011,
TH = 1100,
TH = 1101,
TH = 1110,
TH = 1111
Sunlight Cancellation
DC Current, PD I
DC
100 PA Vcc = 3.0 V
[1]
Note:
1. Specified by design, not production tested.
5
Typical Application Circuit
V
CC
R2
V
CC
MCU APDS-9702
1
2
3
4
SDA
SCL
DOUT
8
5
6
7
Reflective Object
LEDA
PFILT
PDGND
R1
R3 (Optional)
CX1 CX2
CX3
Avago
Proximity Sensor
RpRp
ADC
GPIO
SDA
SCL
(Optional)
Figure 2. Typical Application Circuit for APDS-9702
Recommended Avago
Proximity Sensor Description
HSDL-9100 Integrated Reflective Proximity Sensor
Component Recommended Values ( with HSDL-9100)
R1 10 : ± 5%, 0.25W
R2 10k: ± 5%
R3 1M: ± 5%
Rp 10k: ± 5%
CX1 100 nF ± 20% X 7R, Ceramic,
CX2 6.8 PF ± 20%, Tantalum
CX3 3.3 nF ± 20% X 7R, Ceramic
6
I
2
C Definition
APDS-9702 operates as slave device on I
2
C bus for clock frequency (SCL) up to 400 kHz. The basic protocol of I
2
C bus is
described below, for more details and specifications, please refer to I
2
C-bus specification and user manual.
SCL
SDA
SP
START condition STOP condition
START and STOP conditions
SDA
SCL
1728
acknowledgement
signal from slave
MSB
START or
repeated START
condition
byte complete,
interrupt within slave
S or Sr
ACK
clock line held LOW while
interrupts are serviced
ACK
9
Sr or P
1 2 3 to 8 9
acknowledgement
signal from receiver
STOP or
repeated START
condition
Sr
P
1 2 3 to 8 9
ACK
MSB MSB
Data transfer on I
2
C bus
SCL
SDA
S
START
condition
ADDRESS
1-7 8 9 1-7 8 9 1-7 8 9
P
STOP
condition
ACKDATA
High byte
DATA
Low byte
ACKACK
W
A complete data transfer
1 7 1181811
S Slave Address Wr A Data Byte A Data Byte A P
S Start Condition
Wr Write”0”
A Acknowledge (0 for ACK)
P Stop Condition
Master-to-Slave
Slave-to-Master
Slave Address: 1010100 (Default)

APDS-9702-020

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Proximity Sensors Sigl Conditioning IC f/ Opt Proximity Sen
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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