12
Figure 22. Example printed circuit board layout.
PC Board Layout
The design of the printed circuit board (PCB) should follow
good layout practices, such as keeping bypass capacitors
close to the supply pins, keeping output signals away from
input signals, the use of ground and power planes, etc. In
addition, the layout of the PCB can also aect the isolation
transient immunity (CMTI) of the ACPL-C79B/C79A/C790,
due primarily to stray capacitive coupling between the
input and the output circuits. To obtain optimal CMTI
performance, the layout of the PC board should minimize
any stray coupling by maintaining the maximum possible
distance between the input and output sides of the circuit
and ensuring that any ground or power plane on the PC
board does not pass directly below or extend much wider
than the body of the ACPL-C79B/C79A/C790. Figure 22
shows an example PCB layout.
TO GND1 TO V
DD1
C4
TO V
DD2
TO GND2
V
OUT+
V
OUT–
TO R
SENSE+
TO R
SENSE–
C2
Note: Drawing not to scale
U2
ACPL-C79B/C79A/C790
Shunt Resistor Selection
The current sensing resistor should have low resistance (to
minimize power dissipation), low inductance (to minimize
di/dt induced voltage spikes which could adversely
aect operation), and reasonable tolerance (to maintain
overall circuit accuracy). Choosing a particular value for
the resistor is usually a compromise between minimiz-
ing power dissipation and maximizing accuracy. Smaller
sense resistance decreases power dissipation, while larger
sense resistance can improve circuit accuracy by utilizing
the full input range of the ACPL-C79B/C79A/C790.
Application Information
Application Circuit
The typical application circuit is shown in Figure 21. A
oating power supply (which in many applications could
be the same supply that is used to drive the high-side
power transistor) is regulated to 5 V using a simple three-
terminal voltage regulator (U1). The voltage from the
current sensing resistor, or shunt (R
SENSE
), is applied to
the input of the ACPL-C79B/C79A/C790 through an RC
anti-aliasing lter (R5 and C3). And nally, the dierential
output of the isolation amplier is converted to a ground-
referenced single-ended output voltage with a simple
dierential amplier circuit (U3 and associated com-
ponents). Although the application circuit is relatively
simple, a few recommendations should be followed to
ensure optimal performance.
Power Supplies and Bypassing
As mentioned above, an inexpensive 78L05 three-terminal
regulator can be used to reduce the gate-drive power
supply voltage to 5 V. To help attenuate high frequency
power supply noise or ripple, a resistor or inductor can
be used in series with the input of the regulator to form a
low-pass lter with the regulator’s input bypass capacitor.
The power supply for the isolation amplier is most
often obtained from the same supply used to power the
power transistor gate drive circuit. If a dedicated supply
is required, in many cases it is possible to add an addi-
tional winding on an existing transformer. Otherwise,
some sort of simple isolated supply can be used, such as
a line powered transformer or a high-frequency DC-DC
converter.
As shown in Figure 21, 0.1 µF bypass capacitors (C2, C4)
should be located as close as possible to the pins of the
isolation amplier. The bypass capacitors are required
because of the high-speed digital nature of the signals
inside the isolation amplier. A 47 nF bypass capacitor
(C3) is also recommended at the input pins due to the
switched-capacitor nature of the input circuit. The input
bypass capacitor also forms part of the anti-aliasing lter,
which is recommended to prevent high-frequency noise
from aliasing down to lower frequencies and interfering
with the input signal. The input lter also performs an
important reliability function – it reduces transient spikes
from ESD events owing through the current sensing
resistor.
