XLP53V622.080000I Datasheet XLP53V016.000000I, XLP53V030.000000X, XLP53V065.000000X | P4-P6

FVXO-PC53 Series

Page 4 of 15

Output Wave Characteristics

Parameters

Symbol

Condition

Maximum Value

(unless otherwise noted)

Low Output Voltage V

OL

0.75 MHz to 1.35 GHz 1.305V ~ 1.65V

High Output Voltage V

OH

0.75 MHz to 1.35 GHz 2.055V ~ 2.405V

Typical Complementary Difference V

P-P

0.75 MHz to 1.35 GHz 0.750 V

P-P

Typ

Output Symmetry (See Drawing Below) @ 50% V

P-P

Level 45% ~ 55%

Output Enable

(

PIN # 2

)

Voltage V

IH

> 70% V

DD

Output Disable

(PIN # 2)

Voltage V

IL

< 30% V

DD

Cycle Rise Time (See Drawing Below) T

R

0.75 MHz to 1.35 GHz 400 pS

(20%~80%)

Cycle Fall Time

(See Drawing Below) T

F

0.75 MHz to 1.35 GHz 400 pS

(80%~20%)

Period

1/2 Period

OUTPUT 1

OUTPUT 2

Oscillator Symmetry

20% to 80%

DD

50% V

Rise Time / Fall Time Measurements

Ideally, Symmetry should be 50/50 for 1/2 period -- Other expressions are 45/55 or 55/45

R

T

F

T

OUTPUT 1

OUTPUT 2

2.055V ~ 2.405V

1.305V ~ 1.65V

2.055V ~ 2.405V

1.305V ~ 1.65V

FVXO-PC53 Series

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Jitter is frequency dependent. Below are typical values at select frequencies.

Phase Jitter is integrated from HP3048 Phase Noise Measurement System; measured directly into 50 ohm input; V

DD

= 3.3V.

TIE

was measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software; V

DD

= 3.3V.

Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)

Rj and Dj, measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software.

Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)

LVPECL Phase Jitter & Time Interval Error (TIE)

Frequency

Phase Jitter

(12kHz to 20MHz)

T I E

(Sigma of Jitter Distribution)

Units

62.5 MHz 1.01 3.1 pS RMS

156.25 MHz 0.86 3.5 pS RMS

212.5 MHz 1.05 3.6 pS RMS

622.08MHz

0.94

3.5

pS RMS

LVPECL Random & Deterministic Jitter Composition

Frequency

Random (Rj)

(pS RMS)

Deterministic (Dj)

(pS P-P)

Total Jitter (Tj)

(14 x Rj) + Dj

62.5 MHz 1.27 8.1 26.2 pS

156.25 MHz 1.29 9.3 27.7 pS

212.5 MHz 1.22 8.6 26.1 pS

622.08 MHz

1.21

9.6

26.8 pS

Phase Noise

Offset Frequenc

y

(

10Hz to 40MHz

)

(dBc / Hz) vs. offset frequency

Phase Noise Graph

1k

-110dBc

-120dBc

-130dBc

-150dBc

-140dBc

-160dBc

10 100

-100dBc

-60dBc

-80dBc

-90dBc

-70dBc

-40dBc

-50dBc

-30dBc

-20dBc

-10dBc

0 dBc

1M10k 100k

FOUR frequencies matching

10M 40M

62.5 MHz

212.5 MHz

622.08 MHz

62.5 MHz

622.08 MHz

212.5 MHz

156.25MHz

Data Collected using HP 3048A

the below jitter measurements

FVXO-PC53 Series

Page 6 of 15

Pin Description and Recommended Circuit

Pin #

Name

Type

Function

1 V

C

Control Frequency Control by changing voltage

2

E / D

1

Logic Enable / Disable Control of Output (0 = Disabled)

3 GND Ground Electrical Ground for V

DD

4 Output Output LVPECL Oscillator Output

5 Output 2 Output Complementary LVPECL Output

6

V

DD

2

Power Power Supply Source Voltage

NOTES:

1

Includes pull-up resistor to V

DD

to provide output when the pin (2)is No Connect.

2

Installation should include a 0.01µF bypass capacitor placed between V

DD

(Pin 6)and GND (Pin 3) to minimize power supply line noise.

V

C

V

DD

E / D Output 2

GND Output

Terminations as viewed from the Top

Enable / Disable Control

Pin # 2 (state) Output (Pin # 4, Pin # 5)

OPEN

(No Connection)

ACTIVE Output

“1” Level V

IH

> 70% V

DD

ACTIVE Output

“0” Level V

IL

< 30% V

DD

High Impedance

Soldering Reflow Profile (2 times Maximum at 260°C for 10 seconds MAX)

25°C

160°C

180°C

225°C

260°C

10 Seconds Max

within 5°C of 260°C peak

Ramp Down

Not to exceed 6°C/s

Ramp-Up

3°C/s Max

p

t

120 ± 20 Seconds

In Pre-heating Area

Above 225°C Reflow Area

50±10 Seconds

400 Seconds MAX from +25°C to 260°C peak

# 5# 2E / D

V -2V = +1.3V

GND

DD

# 3 # 4

LVPECL OUTPUT

0.01 F

50

# 1 # 6

LVPECL OUTPUT2

0.01 F

V +3.3V

DD

V

C

3

1

4

6

2

5

XLP53V622.080000I

XLP53V622.080000I

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