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ISL54004IRTZ-T

P1-P3P4-P6P7-P9P10-P12P13-P13
7
FN6513.2
October 30, 2007
The “Typical Application Circuit and Block Diagram” for this
device is provided on page 6. The “Truth Table” for the
device is provided on page 2.
DC Bias Voltage
The ISL54004 has internal DC bias circuitry which DC
offsets the incoming audio signal at V
DD
/2. When using a 5V
supply, the DC offset will be 2.5V. When using a 3.6V supply
the DC offset will be 1.8V.
Since the signal gets biased internally at V
DD
/2 the audio
signals need to be AC coupled to the inputs of the device.
The value of the AC coupling capacitor depends on the low
frequency range required for the application. A capacitor of
0.22µF will pass a signal as low as 7.2Hz. The formula
required to calculate the capacitor value is shown in
Equation 1:
The 100k is the impedance looking into the input of the
ISL54004 device.
BTL Speaker Amplifier
The ISL54004 contains one bridge-tied load (BTL) amplifier
designed to drive an 8 speaker load differentially. The
output to the BTL amplifier are SPK+ and SPK-. The
speaker load gets connected across these terminals.
A single BTL driver consists of an inverting and non-inverting
power op amps. The AC signal out of each op amp are equal
in magnitude but 180° out-of-phase, so the AC signal at
SPK+ and SPK- have the same amplitude but are 180°
out-of-phase.
Driving the load differentially using a BTL configuration
doubles the output voltage across the speaker load and
quadruples the power to the load. In effect you get a gain of
two due to this configuration at the load as compared to
driving the load with a single-ended amplifier with its load
connected between a single amplifier’s output and GND.
The outputs of the BTL are biased at V
DD
/2. When the load
gets connected across the + and - terminal of the BTL the
mid supply DC bias voltage at each output gets cancelled
out eliminating the need for large bulky output coupling
capacitors.
Headphone (Single-Ended) Amplifiers
The ISL54004 contains two single-ended (SE) headphone
amplifiers for driving the left and right channels of a 32 or
16 headphone speakers.
One SE amplifier drives the right speaker of the headphone
and other SE amplifier drives the left speaker of the
headphone. The speaker load gets connected between the
output of the amplifier and ground.
The audio signal at the output of each SE driver is biased at
V
DD
/2 and unlike the BTL driver that cancels this offset due
to its differential connection, a capacitor is required at the
output of each SE drivers to remove this DC voltage from the
headphone load.
This coupling capacitor along with the resistance of the
speaker load creates a high pass filter that sets the
amplifier’s lower bandpass frequency limit. The value of this
AC coupling capacitor depends on the low frequency range
required for the application. The formula required to
calculate the capacitor value is shown in Equation 2:
For an application driving a 32 headphone with a lower
frequency requirement of 150Hz the required capacitor value
is shown in Equation 3:
Use the closest standard value.
Headphone Sense Function
With a logic “1” at the HP control pin while the HO control pin
is low will activate the headphone drivers and disable the
BTL driver.
The “ISL54004 Typical Application Circuit and Block
Diagram” on page 6 shows the implementation of the
headphone control function using a common headphone
jack.
The HP pin gets connected to the mechanical wiper blade of
the headphone jack. Two external resistors are required for
proper operation. A 100k pull-up resistor from the HP pin to
VDD and a 10k pull-down resistor from the jack’s audio
signal pin to GND of the jack signal pin to which the wiper is
connected. See “ISL54004 Typical Application Circuit and
Block Diagram” on page 6.
When no headphone plug is inserted into the jack the
voltage at the HP pin gets set at a low voltage level due to
the 10k resistor and 100k resistor divider network
connection to V
DD
.
When a headphone is inserted into the jack the 10k
resistor gets disconnected from the HP control pin and the
HP pin gets pulled up to V
DD
. Since the HP pin is now high
the headphone drivers are activated.
A microprocessor or a switch can be used to drive the HP
pin rather than using the headphone jack contact pin.
Note: With a logic “1” at the HO pin the BTL driver remains
active regardless of the voltage level at the HD pin. This
allows a headphone to be plugged into the headphone jack
without activating the HP drivers. Music will continue to play
through the internal 8 speaker rather than the headphones.
ISL54004
8
FN6513.2
October 30, 2007
Low Power Shutdown
With a logic “1” at the SD control pin the device enters the
low power shutdown state. When in shutdown the BTL and
headphone amplifiers go into an high impedance state and
I
DD
supply current is reduced to 26µA (typ).
In shutdown mode before the amplifiers enter the high
impedance/low current drive state, the bias voltage of V
DD
/2
remains connected at the output of the amplifiers through a
100k resistor.
This resistor is not present during active operation of the
drivers but gets switched in when the SD pin goes high. It
gets removed when the SD pin goes low.
Leaving the DC bias voltage connected through a 100k
resistor while going into and out of shutdown reduces the
transient at the speakers to a small level preventing clicking
or popping in the speakers.
Note: When the SD pin is High it overrides all other logic
pins.
QFN Die Attach Paddle Considerations
The QFN package features an exposed thermal pad on its
underside. This pad lowers the package’s thermal resistance
by providing a direct heat conduction path from the die to the
PCB. Connect the exposed thermal pad to GND by using a
large copper pad and multiple vias to the GND plane. The
vias should be plugged and tented with plating and solder
mask to ensure good thermal conductivity.
Best thermal performance is achieved with the largest
practical copper ground plane area.
PCB Layout Considerations and Power
Supply Bypassing
To maintain the highest load dissipation and widest output
voltage swing the power supply PCB traces and the traces
that connect the output of the drivers to the speaker loads
should be made as wide as possible to minimize losses due
to parasitic trace resistance.
Proper supply bypassing is necessary for high power supply
rejection and low noise performance. A filter network
consisting of a 10µF capacitor in parallel with a 0.1µF
capacitor is recommended at the voltage regulator that is
providing the power to the ISL54004 IC.
Local bypass capacitors of 0.1µF should be put at each V
DD
pin of the ISL54004 device. They should be located as close
as possible to the pin, keeping the length of leads and traces
as short as possible.
A 1µF capacitor from the REF pin (pin 10) to GND is needed
for optimum PSRR and internal bias voltage stability.
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified
FIGURE 1. THD+N vs FREQUENCY
FIGURE 2. THD+N vs FREQUENCY
ISL54004
9
FN6513.2
October 30, 2007
FIGURE 3. THD+N vs OUTPUT POWER FIGURE 4. THD+N vs OUTPUT POWER
FIGURE 5. THD+N vs FREQUENCY
FIGURE 6. THD+N vs FREQUENCY
FIGURE 7. THD+N vs FREQUENCY
FIGURE 8. THD+N vs FREQUENCY
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified (Continued)
ISL54004
P1-P3P4-P6P7-P9P10-P12P13-P13

ISL54004IRTZ-T

Mfr. #:
Buy ISL54004IRTZ-T
Manufacturer:
Renesas / Intersil
Description:
Audio Amplifiers MONO 1 1 W/INTEGRTD SUBSYSTEM W/STEREO
Lifecycle:
New from this manufacturer.
Delivery:
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