RangeMAX™ LX1688
PRODUCTION DATA SHEET
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 7
Copyright © 2001
Rev. 1.2, 2006-03-09
WWW.Microsemi .COM
Multiple Lamp CCFL Controller
TM
®
DETAILED DESCRIPTION
The LX1688 is a backlight controller specifically
designed with a special feature set needed in multiple lamp
desktop monitors, and other multiple lamp displays. While
utilizing the same architecture as Microsemi’s LX1686
controller it eliminates the synchronized digital dimming
and adds, lamp ‘strike’ count out timer, lamp fault status
output, and external clock input/output that permits multiple
controllers to synchronize their output current both in
frequency and phase.
O
PERATION FROM 3.3V AND/OR 5.0V INPUT SUPPLY
The LX1688 is designed to operate and meet all
specifications at 3.3V ±10% to 5.0V ±10%. The under
voltage lockout is set at nominally 2.8V with a 190mV
hysteresis.
M
ASTER/SLAVE CLOCK SYNCHRONIZATION
One or more controllers (up to 11) may be designated as
slave controllers and receive ramp reset and phase
synchronization from the designated master controller.
This will allow up to 12 lamps (24 with two lamps in
series/controller design) to all operate in phase and
frequency synchronization. This is important to prevent
random interference between lamps through unpredictably
changing electric and magnetic fields that will inevitably
link them.
The LX1688 has two independent oscillators, one for
lamp strike and one for the lamp run frequency. The strike
oscillator ramps the operating frequency slowly up and
down when the open lamp sense input (OLSNS) indicates
the lamp is not ignited. During this lamp strike condition
the operating frequency of each IC will vary up and down
as needed to strike its lamp. The controller is so designed
that the master controller clock remains at the pre-selected
frequency for fully ignited lamps even while striking.
Likewise the designated slave controller will not alter the
frequency or phase of the master clock during its strike
phase. Thus each controller will vary its frequency as
needed to strike its lamp then it will synchronize to the
master clock frequency and phase.
The TRI_C wave generator (see Block Diagram) sets the
rate of operating frequency variation during lamp strike.
The TRI_C generator is connected to a 6-bit counter that
times out after 63 cycles and then latches the FAULT
output high if the OLSNS input indicates no lamp current is
flowing. Even in the case of timeout fault the master
controller clock will continue to provide synchronization to
the slave controllers.
When synchronizing more than one controller the Ramp
Reset (RMP_RST), Phase Sync (PHA_SYNC),
and Slave Input/Output are used. RMP_RST and
PHA_SYNC should be connected between all the
controllers. The master controller should have its SLAVE
pin connected to VSS (GND) and the slave controllers
SLAVE input to VDD (High).
BEPOL
INPUT
The BEPOL pin is a tri-mode input that controls the
polarity of the ENABLE and BRITE input signals.
Depending on the state of this pin (VDD, floating, or VSS)
the controller can be set to allow active high enable with
active high full brightness or active high or low enable
with active low full brightness (see Table 1).
BRITE
INPUT (DIMMING INPUT)
The BRITE input is capable of accepting either a DC
voltage (>
.5V to < 2.5V) or a PWM digital signal that is
clamped on chip (< .5V or > 2.5V). A digital signal can
either be passed unfiltered to effect pulse ‘digital’ dimming
or filtered with a capacitor to effect analog dimming with a
digital PWM signal.
Analog Dimming Methods:
• Mechanical or digital potentiometer set to provide 1V
to 2.5V on the wiper output. A filter cap from BRITE
to signal ground is recommended.
• D/A converter output directly connected to BRITE
input. A R/C filter using a capacitor from the CPW1
input to ground for applications where the ADC output
may contain noise sufficient to modulate the BRITE
input.
• A high frequency PWM digital logic pulse connected
directly to the BRITE input. The Brightness (BRT,
internal node) output will be sensitive only to the
PWM duty cycle, and not to the PWM signal
amplitude, so long as the amplitude exceeds 2.6V for a
logic high (1) and is less than .4V for a logic (0). This
pulse frequency will typically be between 1KHz and
100KHz and will not be synchronized with the LCD
video frame rate. A capacitor (CPWM) between
CPW1 and CPW2 will integrate the PWM signal for
use by the controller.
Digital Dimming Methods:
• Low frequency PWM digital logic pulses connected
directly to the BRITE input. As above the Brightness
(BRT internal) will be sensitive only to the PWM duty
cycle, and not to the PWM signal amplitude, so long
as the amplitude exceeds 2.6V for a logic high (1) and
is less than .4V for a logic (0). This pulse frequency
will typically be in the range of 90-320Hz.
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