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NCP1082DEG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
NCP1082
http://onsemi.com
7
Recommended Operating Conditions
Operating conditions define the limits for functional operation and parametric characteristics of the device. Note that the
functionality of the device outside the operating conditions described in this section is not warranted. Operating outside the
recommended operating conditions for extended periods of time may affect device reliability.
All values concerning the DC−DC controller, VDDH and VDDL blocks are with respect to ARTN. All others are with respect
to VPORTN
1,2
(unless otherwise noted).
Table 3. OPERATING CONDITIONS
Symbol Parameter Conditions Min Typ Max Unit
INPUT SUPPLY
VPORT
Input supply voltage VPORT = VPORTP −
VPORTN
1,2
0 57 V
SIGNATURE DETECTION
Vsignature
Input supply voltage signature detection range 1.4 9.5 V
Rsignature Signature resistance (Note 4) 23.75 26.25
kW
Offset_current I_VportP + I_Rtn VPORTP = RTN = 1.4 V − 1.8 5
mA
Sleep_current I_VportP + I_Rtn VPORTP = RTN = 9.5 V − 15 25
mA
CLASSIFICATION
Vcl
Input supply voltage classification range 13 20.5 V
Iclass0
Class 0: Rclass 10 kW (Note 5)
Iclass0 = I_VportP + I_Rdet 0 − 4 mA
Iclass1
Class 1: Rclass 130 W (Note 5)
Iclass1 = I_VportP + I_Rdet 9 − 12 mA
Iclass2
Class 2: Rclass 69.8 W (Note 5)
Iclass2 = I_VportP + I_Rdet 17 − 20 mA
Iclass3
Class 3: Rclass 44.2 W (Note 5)
Iclass3 = I_VportP + I_Rdet 26 − 30 mA
Iclass4
Class 4: Rclass 30.9 W (Note 5)
Iclass4 = I_VportP + I_Rdet 36 − 44 mA
IDC
class
Internal current consumption during
classification (Note 6)
For information only − 600 −
mA
UVLO
Vuvlo_on
Default turn on voltage (VportP rising) UVLO pin tied to
VPORTN
1,2
38 40 V
Vuvlo_off Default turn off voltage (VportP falling) UVLO pin tied to
VPORTN
1,2
29.5 32 − V
Vhyst_int UVLO internal hysteresis UVLO pin tied to
VPORTN
1,2
− 6 − V
Vuvlo_pr UVLO external programming range UVLO pin connected to the
resistor divider (R1 & R2)
AUX pin tied to VPORTN
1,2
For information only
13 − 50 V
Vuvlo_pr_aux UVLO external programming VPORT range
with low auxiliary supply support
UVLO & AUX pins configured
for auxiliary supply support
8.5 − 18 V
Vhyst_ext UVLO external hysteresis UVLO pin connected to the
resistor divider (R1 & R2)
− 15 − %
Uvlo_Filter UVLO on/off filter time For information only − 90 −
mS
AUXILIARY SUPPLY OPERATION – INPUT SUPPLY
Vaux_min1
VPORTP−ARTN voltage at startup
(required for VDDH > VDDH_Por_R)
VAUX rising − No external
load on VDDL & VDDH
8.7 − − V
Vaux_min2 VPORTP−ARTN voltage during PWM opera-
tion (required for VDDH > VDDH_Por_F)
Voltage with respect to
Ivddl_load1 & Ivddh_load1
for the load current conditions
8.5 − − V
4. Test done according to the IEEE 802.3af 2 Point Measurement. The minimum probe voltages measured at the PoE−PD are 1.4 V and 2.4 V,
and the maximum probe voltages are 8.5 V and 9.5 V.
5. Measured with an external Rdet of 25.5 kW between VPORTP and VPORTN
1,2
, and for 13 V < VPORT < 20.5 V (with VPORT = VPORTP
– VPORTN
1,2
). Resistors are assumed to have 1% accuracy.
6. This typical current excludes the current in the Rclass and Rdet external resistors.
NCP1082
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8
Table 3. OPERATING CONDITIONS
Symbol Parameter Conditions Min Typ Max Unit
AUXILIARY SUPPLY OPERATION – AUX PIN
Vaux_off
Voltage range of the AUX pin where the
auxiliary supply circuit is guaranteed not
operational.
Voltage with respect to
VPORTN
1,2.
− − 0.2 V
Vaux_on Voltage range of the AUX pin where the
auxiliary supply circuit is guaranteed
operational.
Voltage with respect to
VPORTN
1,2
1.5 − 3.3 V
Raux Total resistance value of the resistor di-
vider connected to the AUX pin (sum of
R
aux1
and R
aux3
)
Between VAUX supply &
VPORTN
1,2
− − 25
kW
AUXILIARY SUPPLY OPERATION – VDDL REGULATOR
Ivddl_load1
Current load on the VDDL pin with
VPORTP − ARTN = 8.5 V (Notes 7 and 8)
Ivddh_load + Ivddl_load
< 4.5 mA
− − 1 mA
Ivddl_load2 Current load on the VDDL pin with
VPORTP − ARTN > 12.5 V
(Notes 7 and 8)
Ivddh_load + Ivddl_load
< 10 mA
− − 2.25 mA
AUXILIARY SUPPLY OPERATION – VDDH REGULATOR
Ivddh_load1
Current load on the VDDH regulator with
VPORTP − ARTN = 8.5 V (Notes 7 and 8)
Ivddh_load + Ivddl_load
< 4.5 mA
− − 4.5 mA
Ivddh_load2 Current load on the VDDH regulator with
VPORTP − ARTN > 12.5 V
(Notes 7 and 8)
Ivddh_load + Ivddl_load
< 10 mA
− − 10 mA
PASS−SWITCH AND CURRENT LIMITS
Ron
Pass−switch Rds−on Max Ron specified at
T
J
= 130°C
− 0.6 1.2
W
I_Rinrush1
Rinrush = 150 kW (Note 9)
Measured at RTN−
VPORTN
1,2
= 3 V
95 125 155 mA
I_Rinrush2
Rinrush = 57.6 kW (Note 9)
Measured at RTN−
VPORTN
1,2
= 3 V
260 310 360 mA
I_Rilim1
Rilim1 = 84.5 kW (Note 9)
Current limit threshold 450 510 570 mA
INRUSH AND ILIM1 CURRENT LIMIT TRANSITION
Vds_pgood
VDS required for power good status RTN−VPORTNx falling; volt-
age with respect to
VPORTN
1,2
0.8 1 1.2 V
Vds_pgood_hyst VDS hysteresis required for power good
status
Voltage with respect to
VPORTN
1,2
− 8.2 − V
7. Ivddl_load = current flowing out of the VDDL pin.
Ivddh_load = current flowing out of the VDDH pin + current delivered to the Gate Driver (function of the frequency, VDDH voltage & MOSFET
gate capacitance).
8. See Figures 6 and 7 for specifications on the load current at lower or higher VPORTP-ARTN voltages. In case the application requires more
current capability on VDDL and VDDH, it is recommended to externally supply the VDDH pin with a bias winding from the transformer or
to add a diode between VAUX(+) and VDDH pin (verify the VAUX voltage does not exceed the VDDH voltage range).
9. The current value corresponds to the PoE−PD input current (the current flowing in the external Rdet and the quiescent current of the device
are included). Resistors are assumed to have 1% accuracy.
NCP1082
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9
Table 3. OPERATING CONDITIONS
Symbol Parameter Conditions Min Typ Max Unit
VDDH REGULATOR
VDDH_reg
Regulator output voltage
(Notes 10 and 11)
Ivddh_load + Ivddl_load < 10 mA
with Ivddl_load < 2.25 mA and
12.5 V < VPORTP − ARTN < 57 V
8.4 9 9.6 V
VDDH_Off Regulator turn−off voltage For information only − VDDH_reg
+ 0.5 V
− V
VDDH_lim VDDH regulator current limit
(Notes 10 and 11)
13 − 26 mA
VDDH_Por_R VDDH POR level (rising) 7.3 − 8.3 V
VDDH_Por_F VDDH POR level (falling) 6 − 7 V
VDDH_ovlo VDDH over−voltage level (rising) 16 − 18.5 V
VDDL REGULATOR
VDDL_reg
Regulator output voltage
(Notes 10 and 11)
Ivddl_load < 2.25 mA with
Ivddh_load + Ivddl_load < 10 mA
and 12.5 V < VPORTP −
ARTN < 57 V
3.05 3.3 3.55 V
VDDL_Por_R VDDL POR level (rising) VDDL
– 0.2
− VDDL
– 0.02
V
VDDL_Por_F VDDL POR level (falling) 2.5 − 2.9 V
GATE DRIVER
Gate_Tr
GATE rise time (10−90%) Cload = 2 nF, VDDHreg = 9 V − − 50 ns
Gate_Tf GATE fall time (90−10%) Cload = 2 nF, VDDHreg = 9 V − − 50 ns
PWM COMPARATOR
VCOMP
COMP control voltage range For information only 1.3 − 3 V
ERROR AMPLIFIER
Vbg_fb
Reference voltage Voltage with respect to ARTN 1.15 1.2 1.25 V
Av_ol DC open loop gain For information only − 80 − dB
GBW Error amplifier GBW For information only 1 − − MHz
SOFT−START
Vss
Soft−start voltage range − 1.15 − V
Vss_r Soft−start low threshold
(rising edge)
0.35 0.45 0.55 V
Iss Soft−start source current 3 5 7
mA
CURRENT LIMIT COMPARATOR
CSth
CS threshold voltage 324 360 396 mV
Tblank Blanking time For information only − 100 − ns
10.Power dissipation must be considered. Load on VDDH and VDDL must be limited especially if VDDH is not powered by an auxiliary winding.
11. Ivddl_load = current flowing out of the VDDL pin.
Ivddh_load = current flowing out of the VDDH pin + current delivered to the Gate Driver (function of the frequency, VDDH voltage & MOSFET
gate capacitance).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

NCP1082DEG

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Manufacturer:
ON Semiconductor
Description:
Switching Controllers POE-PD 13W DC-DC AUX SUPP
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