CS5464-ISZ Datasheet CS5464-ISZ, CS5464-ISZR, CS5464-IS | P13-P15

CS5464

DS682F3 13

SWITCHING CHARACTERISTICS (Continued)

Notes: 19. Pulse output timing is specified at DCLK = 4.096 MHz, E2MODE = 0, and E3MODE[1:0] = 0. Refer to

6.7 Energy Pulse Outputs on page 19 for more information on pulse output pins.

20. Timing is proportional to the frequency of DCLK.

ABSOLUTE MAXIMUM RATINGS

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes

Notes: 21. VA+ and AGND must satisfy [(VA+) - (AGND)]  + 6.0 V.

22. VD+ and AGND must satisfy [(VD+) - (AGND)]  + 6.0 V.

23. Applies to all pins including continuous over-voltage conditions at the analog input pins.

24. Transient current of up to 100 mA will not cause SCR latch-up.

25. Maximum DC input current for a power supply pin is ±50 mA.

26. Total power dissipation, including all input currents and output currents.

Parameter Symbol Min Typ Max Unit

, E2, and E3 Timing (Note 19 and 20)

Period t

period

500 - - s

Pulse Width t

244 - - s

Rising Edge to Falling Edge t

6--s

Setup to E1 and/or E3 Falling Edge t

1.5 - - s

Falling Edge to E3 Falling Edge t

248 - - s

Parameter Symbol Min Typ Max Unit

DC Power Supplies

(Notes 21 and 22)

Positive Digital

Positive Analog

VD+

VA+

-0.3

+6.0

Input Current, Any Pin Except Supplies

(Notes 23, 24, 25) I

--±10mA

Output Current, Any Pin Except VREFOUT I

OUT

--100mA

Power Dissipation

(Note 26) PD --500mW

Analog Input Voltage

All Analog Pins V

INA

- 0.3 - (VA+) + 0.3 V

Digital Input Voltage

All Digital Pins V

IND

-0.3 - (VD+) + 0.3 V

Ambient Operating Temperature T

-40 - 85 °C

Storage Temperature T

stg

-65 - 150 °C

period

Figure 2. Timing Diagram for E1, E2, and E3

CS5464

14 DS682F3

4. SIGNAL PATH DESCRIPTION

The data flow for voltage and current measurement and

the other calculations are shown in Figures 3, 4, and 5.

The data flow consists of two current

paths and two volt-

age

paths. Both voltage paths are derived from the

same differential input pins. Each current path has its

own differential input pins.

4.1 Analog-to-Digital Converters

The voltage and temperature channels use second-or-

der delta-sigma modulators and the two current chan-

nels use fourth-order delta-sigma modulators to convert

the analog inputs to single-bit digital data streams. The

converters sample at a rate of DCLK/8. This high sam-

pling provides a wide dynamic range and simplifies an-

ti-alias filter design.

4.2 Decimation Filters

The single-bit modulator output data is widened to

24 bits and down-sampled to DCLK/1024 with low-pass

decimation filters. These decimation filters are third-or-

der Sinc. Their outputs are passed through third-order

IIR “anti-sinc” filters, used to compensate for the ampli-

tude roll-off of the decimation filters.

4.3 Phase Compensation

Phase compensation changes the phase of current rel-

ative to voltage by changing the sampling time in the

decimation filters. The amount of phase shift is set by

bits PC[7:0] in the Configuration register

(Config) for

channel 1 and bits PC[7:0] in the Control register (

Ctrl)

for channel 2.

Phase compensation, PC[7:0] is a signed two’s comple-

ment binary value in the range of -1.0 to almost +1.0

output word rate (OWR) samples. For a sample rate of

4000 Hz, the delay range is ±250

S, a phase shift of

±4.5° at 50 Hz and ±5.4° at 60 Hz. The step size would

be 0.0352° at 50 Hz and 0.0422° at 60 Hz at this sample

rate.

Figure 3. Signal Flow for V1, I1, P1, Q1 Measurements

FGA

OFF

GAIN

OFF

GAIN

Figure 4. Signal Flow for V2, I2, P2, Q2 Measurements

OFF

GAIN

OFF

GAIN

CS5464

DS682F3 15

4.4 DC Offset and Gain Correction

The system and chip inherently have gain and offset er-

rors which can be removed using the gain and offset

registers. (See Section 9.

System Calibration on page

39). Each measurement channel has its own registers.

For every channel, the output of the IIR filter is added to

the offset register and multiplied by the gain register.

4.5 High-pass Filters

Optional high-pass filters (HPF in Figures 3 and 4) re-

move any DC from the selected signal paths. Subse-

quently, DC will also be removed from power, and all

low-rate results. (see Figures 5).

Each energy channel has a current and voltage path. If

an HPF is enabled in only one path, a phase-matching

filter (PMF) is applied to the other path which matches

the amplitude and phase delay of the HPF in the band

of interest, but passes DC. For more information, see

6.5

High-pass Filters on page 19. The HPF filter multi-

plexers drive the

I1, V1, I2, and V2 result registers.

4.6 Low-Rate Calculations

Low-rate results are derived from sample-rate results

integrated over

N samples, where N is the value stored

in the Cycle Count register. The low-rate interval is the

sample interval multiplied by

4.7 RMS Results

The root mean square (RMS in Figure 5) calculations

are performed on

N instantaneous voltage and current

samples, using the formula:

RMS

n0=

N1–



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P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P46

CS5464-ISZ

Mfr. #:

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Cirrus Logic

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Current & Power Monitors & Regulators 3-Ch Single Phase Power/Energy IC

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CS5464-ISZ

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