Data Sheet HMC674LC3C/HMC674LP3E
Rev. K | Page 7 of 14
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
12
11
10
1
3
4 9
2
6
5
7
8
16
15
14
13
VTP
INP
INN
VTN
V
CCO
V
EE
HYS
RTN
V
CCI
Q
Q
V
CCO
V
CCI
LE
LE
NIC
V
EE
PACKAGE
BASE
NOTES
1. NIC = NOT INTERNALLY CONNECTED. CONNECT
THIS PIN TO GROUND FOR IMPROVED NOISE.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO V
EE
.
HMC674LC3C
TOP VIEW
(Not to Scale)
14861-003
Figure 3. HMC674LC3C Pin Configuration
12
11
10
1
3
4 9
2
6
5
7
8
16
15
14
13
VTP
INP
INN
VTN
V
CCO
V
EE
HYS
RTN
V
CCI
Q
Q
V
CCO
V
CCI
LE
LE
NIC
HMC674LP3E
TOP VIEW
(Not to Scale)
V
EE
PACKAGE
BASE
NOTES
1. NIC = NOT INTERNALLY CONNECTED. CONNECT
THIS PIN TO GROUND FOR IMPROVED NOISE.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO V
EE
.
14861-004
Figure 4. HMC674LP3E Pin Configuration
Table 8. HMC674LC3C/HMC674LP3E Pin Function Descriptions
Pin No. Mnemonic Description
1 VTP Termination Resistor Return Pin for V
P
Input. See Figure 5 for the interface schematic.
2 INP Noninverting Analog Input. See Figure 5 for the interface schematic.
3 INN Inverting Analog Input. See Figure 5 for the interface schematic.
Termination Resistor Return Pin for V
N
Input. See Figure 5 for the interface schematic.
CCI
Positive Supply Voltage Input Stage. See Figure 6 for the interface schematic.
6
LE
Latch Enable Input Pin, Inverting Side. See the Theory of Operation section for additional information. See
Figure 6 for the interface schematic.
7 LE Latch Enable Input Pin, Noninverting Side. See the Theory of Operation section for additional information. See
Figure 6 for the interface schematic.
8 NIC Not Internally Connected. Connect this pin to ground for improved noise.
9, 12 V
CCO
Positive Supply Voltage for the Output Stage. See Figure 7 for the interface schematic.
10
Q
Inverting Output.
Q
is at logic low if the analog voltage at the noninverting input, INP, is greater than the
analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of
Operation section for additional information. See Figure 7 for the interface schematic.
11 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, INP, is greater than the
analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of
Operation section for additional information. See Figure 7 for the interface schematic.
13 V
EE
Negative Power Supply, −3 V. See Figure 6 for the interface schematic.
14 HYS Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect this pin to V
EE
with a resistor to add
the desired amount of hysteresis. See Figure 12 to determine the correct size of the R
HYS
hysteresis control resistor.
See Figure 8 for the interface schematic.
15 RTN Return for ESD Protection.
EPAD Exposed Pad. The exposed pad must be connected to V
EE
.
