13
LTC1416
APPLICATIONS INFORMATION
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0000 0000 00 and 1111 1111 1111 11. For full-scale
adjustment, an input voltage of 2.499544V (FS/2 – 1.5LSB)
is applied to A
IN
and R2 is adjusted until the output code
flickers between 0111 1111 1111 10 and 0111 1111
1111 11.
applications, however, do not have a –5V supply readily
available and most ADCs have inadequate PSRR to suffi-
ciently attenuate the noise created by a switching or
charge pump supply. The LTC1416’s excellent PSRR
makes it possible to achieve good performance, even at 14
bits, using a switch based regulator for a –5V supply.
Figure 12a shows a circuit using an LT1373 configured as
a Cuk converter creating –5V from a 5V supply. The circuit
shown in Figure 12b uses an LT1054 regulated charge
pump to provide –5V. This circuit has the advantage of
reduced board space and fewer passive components. (For
further details refer to
Linear Technology
Magazine, June
1997, Page 29.)
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1416, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
An analog ground plane separate from the logic system
ground should be established under and around the ADC
(see Figure 13). Pin 5 (AGND), Pins 14 and 19 (ADC’s
DGND) and all other analog grounds should be connected
to this single analog ground point. The REFCOMP bypass
capacitor and the DV
DD
bypass capacitor should also be
connected to this analog ground plane. No other digital
grounds should be connected to this analog ground plane.
Low impedance analog and digital power supply common
returns are essential to low noise operation of the ADC and
the foil width for these tracks should be as wide as
possible. In applications where the ADC data outputs and
control signals are connected to a continuously active
microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough
from the microprocessor to the successive approximation
comparator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or by
using three-state buffers to isolate the ADC data bus. The
1416 F11a
011...111
011...110
000...001
000...000
111...111
111...110
100...001
100...000
FS – 1LSB
(FS – 1LSB)
INPUT VOLTAGE (A
IN
+
– A
IN
)
OUTPUT CODE
Figure 11a. LTC1416 Transfer Characteristics
ANALOG
INPUT
1416 F11b
1
2
3
R4
100
R2
50k
R3
24k
–5V
R6
24k
R1
50k
R5
47k
4
5
22µF
A
IN
+
A
IN
V
REF
REFCOMP
AGND
LTC1416
Figure 11b. Offset and Full-Scale Adjust Circuit
Generating a –5V Supply
There are several advantages to using ±5V supplies rather
than a single 5V supply. A larger signal magnitude is
possible which increases the dynamic range and
improves the signal-to-noise ratio. Operating on ±5V
supplies also offers increased headroom which eases the
requirements for signal conditioning circuitry, avoids the
limitations of rail-to-rail operation and widens the selec-
tion of high performance operational amplifiers. Some
14
LTC1416
APPLICATIONS INFORMATION
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Figure 12b. Using the LT1054 to Generate a –5V Supply
+
+
281
272
263
254
24
C7
1µF CER
C5
C6
5V
–5V
ANALOG
INPUT
LTC1416
5
236
22
MICROPROCESSOR/
MICROCONTROLLER
INTERFACE
7
218
209
1910
1811
1712
1613
1514
C1
10µF
TANT
V
+
FB/SHDN
1
V
REF
6
OSC
7
8
CAP
+
2
GND
3
V
OUT
5
CAP
4
U1
LT1054
R2, 120k
R1, 30.1k
C3
0.002µF
C4
100µF
TANT
C2
2µF
C5 = 22µF CERAMIC
C6, C7 = 10µF CERAMIC
BUSY
CS
CONVST
RD
SHDN
D0
D1
D2
D3
D4
D5
AV
DD
DV
DD
V
SS
COMP
AGND
D13 (MSB)
D12
D11
D10
D9
D8
D7
D6
DGND
A
IN
+
A
IN
V
REF
1416 F12b
+
+
AV
DD
281
DV
DD
272
V
SS
263
BUSY
254
CS
24
C7
1µF CER
C5
C8
22µF
10V
TANT
C6
5V
–5V
1416 F12a
ANALOG
INPUT
LTC1416
5
CONVST
236
RD
22
MICROPROCESSOR/
MICROCONTROLLER
INTERFACE
7
SHDN
218
D0
209
D1
1910
D2
1811
D3
1712
D4
1613
D5
15
A
IN
+
A
IN
V
REF
COMP
AGND
D13 (MSB)
D12
D11
D10
D9
D8
D7
D6
DGND
14
V
SW
1
2
4
3
L1
V
IN
5
NFB
3
8
S/S
4
GND
7
V
C
C9
0.01µF
D1
R3
4.99k
R5
4.99k
1%
R6
499
1%
R4
4.99k
1%
C11
100µF
10V
TANT
C12
0.1µF
1
GND S
6
U2
LT1373
C10
10µF
CER
CUK*
CONVERTER
C5 = 22µF CERAMIC
C6, C7 = 10µF CERAMIC
L1 = OCTAPAC CTX-100-1
D1 = 1N5818
Figure 12a. Using the LT1373 to Generate a –5V Supply
15
LTC1416
APPLICATIONS INFORMATION
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Figure 13. Power Supply Grounding Practice.
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC1416 has differential inputs to minimize noise
coupling. Common mode noise on the A
IN
+
and A
IN
leads
will be rejected by the input CMRR. The A
IN
input can be
used as a ground sense for the A
IN
+
input; the LTC1416
will hold and convert the difference voltage between A
IN
+
and A
IN
. The leads to A
IN
+
(Pin 1) and A
IN
(Pin 2) should
be kept as short as possible. In applications where this is
not possible, the A
IN
+
and A
IN
traces should be run side
by side to equalize coupling.
Supply Bypassing
High quality, low series resistance ceramic, bypass
capacitors should be used at the V
DD
(10µF) and REFCOMP
(22µF) pins as shown in the Typical Application on the first
page of this data sheet. Surface mount ceramic capacitors
such as Murata GRM235Y5V106Z016 provide excellent
bypassing in a small board space. Alternatively tantalum
capacitors in parallel with 0.1µF ceramic capacitors can be
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Example Layout
Figures 14a, 14b, 14c and 14d show the schematic and
layout of an evaluation board. The layout demonstrates the
proper use of decoupling capacitors and ground plane
with a 2-layer printed circuit board.
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a con-
version.
Internal Clock
The A/D converter has an internal clock that eliminates the
need for synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 1.8µs, and a maximum conversion time over the
full operating temperature range of 2.2µs. No external
adjustments are required. The guaranteed maximum
acquisition time is 400ns. In addition, a throughput time
of 2.5µs and a minimum sampling rate of 400ksps is
guaranteed.
Power Shutdown
The LTC1416 provides two power shutdown modes—nap
mode and sleep mode to save power during inactive
periods. The nap mode reduces the power by 95% and
leaves only the digital logic and reference powered up. The
wake-up time from nap to active is 400ns. In sleep mode,
the reference is shut down and only a small current of
120µA remains. Wake-up time from sleep mode is much
slower since the reference circuit must power up and
settle to 0.005% for full 14-bit accuracy. Sleep mode
wake-up time is dependent on the value of the capacitor
connected to the REFCOMP (Pin 4). The wake-up time is
20ms with the recommended 22µF capacitor.
1416 F13
10µF 10µF
ANALOG
INPUT
CIRCUITRY
5
4
2
26
28
27
14
1
22µF
DIGITAL
SYSTEM
A
IN
+
AGNDREFCOMP V
SS
AV
DD
LTC1416
DV
DD
DGND
A
IN
+

LTC1416IG#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 400ksps 14-Bit Parallel ADC
Lifecycle:
New from this manufacturer.
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