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UJA1075TW/3V3,118
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P45
P46-P48
P49-P51
P52-P53
UJA1075_2
All informatio
n provided in this d
ocument is subje
ct to legal discl
aimers.
© NXP B.V
. 2010. All rights reserv
ed.
Product data sheet
Rev
. 02 — 27 May 2010
43 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN cor
e system basis chip
[7]
The watchdog will be reset if it is in
window mode and is triggered at
least t
trig(wd)1
, but not more than t
trig(wd)
2
, after the start of the
watchdog period (or in the second half of the watch
dog period).
A system reset will be performed if the watchdog is triggered m
ore than
t
trig(wd)2
after the start of the watchdog period (watchdog overflows).
Fig 15.
Timing test circuit for CAN transceiver
Fig 16.
CAN transceiver timing diagram
SBC
BAT
CANL
CANH
TXDC
R
CANH
−
R
CANL
RXDC
C
RXDC
GND
C
CANH
−
C
CANL
015aaa079
CA
NH
CA
NL
t
d(TXDC-busdom)
TX
D
C
V
O(dif)bus
RXDC
HIG
H
HIG
H
LO
W
LO
W
dominant
r
e
ce
ssive
0.9 V
0.5 V
t
d(busdom-RXDC)
t
d(TXDC-busrec)
t
d(busrec-RXDC)
t
d(TXDCH-RXDCH)
t
d(TXDCL-RXDCL)
015aaa15
1
UJA1075_2
All informatio
n provided in this d
ocument is subje
ct to legal discl
aimers.
© NXP B.V
. 2010. All rights reserv
ed.
Product data sheet
Rev
. 02 — 27 May 2010
44 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN cor
e system basis chip
Fig 17.
Timing test circuit for LIN transceiver
SBC
BAT
DLIN
TXDL
R
LIN
C
LIN
RXDL
C
RXDL
LIN
GND
015aaa12
8
Fig 18.
LIN transceiver timing
diagram
015aaa133
V
TXDL
LIN bus signal
V
BAT
t
bit
t
bus(rec)(min)
V
th(rec)RX(max)
thresholds of
receiving node A
V
th(dom)RX(max)
V
th(rec)RX(min)
V
th(dom)RX(min)
t
PD(RX)r
t
PD(RX)f
t
PD(RX)r
t
PD(RX)f
t
bus(rec)(max)
t
bit
t
bit
thresholds of
receiving node B
output of receiving
node A
V
RXDL
output of receiving
node B
V
RXDL
t
bus(dom)(max)
t
bus(dom)(min)
UJA1075_2
All informatio
n provided in this d
ocument is subje
ct to legal discl
aimers.
© NXP B.V
. 2010. All rights reserv
ed.
Product data sheet
Rev
. 02 — 27 May 2010
45 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN cor
e system basis chip
1
1. T
est
information
1
1.1
Quality information
This product has been qualified in accordance
with the Automotive Electronics
Council
(AEC) standard
Q100 - Failure mechanism b
ased stress
test qualification for integrated
circuits
, and is suitable for use in automotive applicat
ions.
Fig 19.
SPI timing diagram
015aaa04
5
SCS
SCK
SDI
SDO
X
X
X
MSB
LSB
MSB
LSB
t
v(Q)
floating
floating
t
h(D)
t
su(D)
t
clk(L)
t
clk(H)
t
SPILEAD
T
cy(clk)
t
SPILAG
t
WH(S)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P45
P46-P48
P49-P51
P52-P53
UJA1075TW/3V3,118
Mfr. #:
Buy UJA1075TW/3V3,118
Manufacturer:
NXP Semiconductors
Description:
IC SBC CAN/LIN HS 3.3V 32HTSSOP
Lifecycle:
New from this manufacturer.
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