OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

CAT5138SDI-10GT3

P1-P3P4-P6P7-P9P10-P10
CAT5136, CAT5137, CAT5138
http://onsemi.com
4
Table 6. A.C. CHARACTERISTICS
Parameter (see Figure 6) Symbol Min Typ Max Units
Clock Frequency F
SCL
400 kHz
Noise Suppression Time Constant at SCL & SDA Inputs T
I
(Note 9) 50 ns
SCL Low to SDA Data Out and ACK Out t
AA
1
ms
Time the bus must be free before a new transmission can start t
BUF
(Note 9) 1.2
ms
Start Condition Hold Time t
HD:STA
0.6
ms
Clock Low Period t
LOW
1.2
ms
Clock High Period t
HIGH
0.6
ms
Start Condition Setup Time (for a Repeated Start Condition) t
SU:STA
0.6
ms
Data In Setup Time t
SU:DAT
100 ns
Data in Hold Time t
HD:DAT
0
ms
SDA and SCL Rise Time t
R
(Note 9) 0.3
ms
SDA and SCL Fall Time t
F
(Note 9) 300 ns
Stop Conditions Setup Time t
SU:STO
0.6
ms
Data Out Hold Time t
DH
100 ns
9. This parameter is tested initially and after a design or process change that affects the parameter.
Table 7. CAPACITANCE (T
A
= 25C, f = 1.0 MHz, V
DD
= 5.0 V)
Parameter
Symbol Test Conditions Min Typ Max Unit
Input/Output Capacitance (SDA, SDC) C
I/O
V
I/O
= 0 V (Note 10) 10 pF
10.This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. POWER-UP TIMING (Notes 11, 12)
Symbol Parameter Min Max Units
t
PUR
Power-up to Read Operation 1 ms
t
PUW
Power-up to Write Operation 1 ms
11. This parameter is tested initially and after a design or process change that affects the parameter.
12.t
PUR
and t
PUW
are the delays required from the time V
DD
is stable until the specified operation can be initiated.
Table 9. WIPER TIMING
Symbol Parameter Min Max Units
t
WRPO
Wiper Response Time After Power Supply Stable 5 10
ms
t
WRL
Wiper Response Time After Instruction Issued 5 10
ms
CAT5136, CAT5137, CAT5138
http://onsemi.com
5
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 2. Resistance between R
W
and R
L
Figure 3. Power Supply Current
TAP POSITION V
CC
(V)
1129680644832160
0
10
20
30
40
50
60
65432
0
10
20
40
50
60
80
90
Figure 4. Integral Non−Linearity Figure 5. Differential Non−Linearity
TAP POSITION TAP POSITION
1129680644832160
−1.0
−0.8
−0.6
−0.2
0
0.4
0.8
1.0
1129680644832160
−1.0
−0.8
−0.4
−0.2
0
0.2
0.6
1.0
R
WL
(kW)
I
CC
(mA)
INL (LSB)
DNL (LSB)
128
128
−0.4
0.2
0.6
128
−0.6
0.4
0.8
30
70
V
CC
= 2.7 V
V
CC
= 5.5 V
Rheostat Configuration
T
A
= +25C, R
POT
= 50 kW
V
CC
= 2.7 V
V
CC
= 5.5 V
Potentiometer Configuration
T
A
= +25C, R
POT
= 10 kW
V
CC
= 2.7 V
V
CC
= 5.5 V
Potentiometer Configuration
−40C
25C
90C
125C
SCL
SDA IN
SDA OUT
Figure 6. Bus Timing
t
SU:STA
t
HD:STA
t
HD:DAT
t
AA
t
F
t
LOW
t
HIGH
t
LOW
t
R
t
SU:DAT
t
DH
t
SU:STO
t
BUF
CAT5136, CAT5137, CAT5138
http://onsemi.com
6
SERIAL BUS PROTOCOL
The following defines the features of the I
2
C bus protocol:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
The device controlling the transfer is a master, typically a
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT513x will be considered a slave device
in all applications.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT513x monitors the SDA and
SCL lines and will not respond until this condition is met
(see Figure 7).
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition (see Figure 7).
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data (see Figure 8).
The CAT513x responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8-bit
byte.
When the CAT513x is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT513x will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
START CONDITION
SDA
STOP CONDITION
SCL
Figure 7. Start/Stop Condition
189
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
Figure 8. Acknowledge Condition
ACK DELAY ( t
AA
)
ACK SETUP ( t
SU:DAT
)
P1-P3P4-P6P7-P9P10-P10

CAT5138SDI-10GT3

Mfr. #:
Buy CAT5138SDI-10GT3
Manufacturer:
ON Semiconductor
Description:
Digital Potentiometer ICs DPP IIC 128 TAPS VOLATILE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet