DVIULC6-4SC6Y

DVIULC6-4SC6Y Technical information
Doc ID 018878 Rev 2 7/12
3.3 How to ensure good ESD protection
While the DVIULC6-4SC6Y provides a high immunity to ESD surge, an efficient protection
depends on the layout of the board. In the same way, with the rail to rail topology, the track
from V
BUS
pin to the power supply +V
CC
, and from V
BUS
pin to GND pin must be as short as
possible to avoid over voltages due to parasitic phenomena (see Figure 13 and Figure 14 for
layout considerations).
Figure 13. IESD behavior: parasitic phenomena due to unsuitable layout
Figure 14. ESD behavior: layout optimization and addition of a 100 nF capacitor
Lw
VI/O
ESD
SURGE
GND
I/O
+V
CC
V
BUS
V
F
Lw
di
dt
Lw
di
dt
V+ =
CL
V +V +Lw
BUS F
di
dt
surge >0
di
dt
surge <0
V- =
CL
-V -Lw
F
t
tr=1ns
VV
CC F
+
Lw
di
dt
V
CL
+
POSITIVE
SURGE
183V
-Lw
di
dt
t
tr=1ns
-V
F
V
CL
-
NEGATIVE
SURGE
-178V
REF1=GND
VI/O
ESD
SURGE
I/O
REF2=+V
CC
C=100nF
Lw
V+ V
CL CC F
V+= surge >0
surge <0
VV
CL F
-- =
t
V+
CL
POSITIVE
SURGE
t
V-
CL
NEGATIVE
SURGE
Technical information DVIULC6-4SC6Y
8/12 Doc ID 018878 Rev 2
Figure 15. PCB layout considerations (V
CC
connection is application dependent)
It’s often harder to connect the power supply near to the DVIULC6-4SC6Y unlike the ground
thanks to the ground plane that allows a short connection.
To ensure the same efficiency for positive surges when the connections can’t be short
enough, we recommend to put close to the DVIULC6-4SC6Y, between V
BUS
and ground, a
capacitance of 100 nF to prevent from these kinds of overfatigue disturbances (see
Figure 14 and Figure 15).
The addition of this capacitance will allow a better protection by providing a constant voltage
during a surge.
Figure 16, Figure 6, and Figure 7 show the improvement of the ESD protection according to
the recommendations described in Section 3.3.
Figure 16. ESD behavior: measurement conditions (with coupling capacitor)
Important
An important precaution to take is to put the protection device as close as possible to the
disturbance source (generally the connector).
D+1
C = 100 nF
D-1
GND
DVIULC6-4SC6
D+2
D-2
V
CC
1
DVI
connector
side
V
cc
(+5V)
C=100 nF
ESD
SURGE
TEST BOARD
DVIULC6-4SC6H
DVIULC6-4SC6Y Technical information
Doc ID 018878 Rev 2 9/12
3.4 Crosstalk behavior
Figure 17. Crosstalk phenomena
The crosstalk phenomena is due to the coupling between 2 lines. The coupling factor (
12
or
21
) increases when the gap across lines decreases, particularly in silicon dice. In the
example above the expected signal on load R
L2
is
2
V
G2
, in fact the real voltage at this point
has got an extra value
21
V
G1
. This part of the V
G1
signal represents the effect of the
crosstalk phenomenon of line 1 on line 2. This phenomenon has to be taken into account
when the drivers impose fast digital data or high frequency analog signals in the disturbing
line. The perturbed line will be more affected if it works with low voltage signal or high load
impedance (few k).
Figure 18. Analog crosstalk measurements
Figure 18 gives the measurement circuit for the analog application. In usual frequency range
of analog signals (up to 240 MHz) the effect on disturbed line is less than -45 dB (see
Figure 8).
As the DVIULC6-4SC6Y is designed to protect high speed data lines, it must ensure a good
transmission of operating signals. The frequency response (Figure 5) gives attenuation
information and shows that the DVIULC6-4SC6Y is well suitable for data line transmission
up to 1.65 Gb/s.
Line 1
Line 2
V
G1
V
G2
R
G1
R
G2
DRIVERS
R
L1
R
L2
RECEIVERS
α
β
+
1
12
V
G1
V
G2
α
β
+
2
21
V
G2
V
G1
SPECTRUM ANALYSER
50 W
TRACKING GENERATOR
Vg
50 W
TEST BOARD
C=100nF
SPECTRUM ANALYSER
V
out
50
Ω
TRACKING GENERATOR
V
g
V
in
50
Ω
TEST BOARD
V
cc
C=100nF
DVIULC6

DVIULC6-4SC6Y

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
TVS Diodes / ESD Suppressors Automotive ultra low capacitance ESD protection
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet