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74LVTN16244BDGG,11
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P17
74L
VTN16244B
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 201
2. All rights rese
rved.
Product data sheet
Rev
. 5 — 2 April 2012
9 of 16
NXP Semiconductors
74L
VTN16244B
3.3 V 16-bit buffer/driver
; 3-st
ate
1
1. W
aveforms
Measurements points are given in
T
able 8
.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 5.
Prop
agation delay
input (nAn) to o
utput (nYn)
mna171
nAn input
nYn output
t
PLH
t
PHL
GND
V
I
V
M
V
M
V
M
V
M
V
OH
V
OL
Measurements points are given in
T
able 8
.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6.
3-
st
ate output enable
and disab
le times
001aae464
t
PZL
nYn output
nYn output
nOE input
V
OL
V
OH
3.0 V
V
I
V
M
GND
0 V
t
PLZ
t
PZH
t
PHZ
V
X
V
Y
V
M
V
M
T
able 8.
Measuremen
t point
s
Input
Output
V
M
V
M
V
X
V
Y
1.5 V
1.5
V
V
OL
+ 0.3 V
V
OH
0.3 V
74L
VTN16244B
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 201
2. All rights rese
rved.
Product data sheet
Rev
. 5 — 2 April 2012
10 of 16
NXP Semiconductors
74L
VTN16244B
3.3 V 16-bit buffer/driver
; 3-st
ate
T
est data is given in
T
able 9
.
Definitions test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe cap
acitance.
R
T
= T
ermination resistance should be equal to output impedance Z
o
of the pulse generator
.
V
EXT
= External voltage for measuring switching times.
Fig 7.
T
est circuit for me
asuring switching tim
es
V
EXT
V
CC
V
I
V
O
001aae235
DUT
C
L
R
T
R
L
R
L
PULSE
GENERATOR
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
T
able 9.
T
est data
Input
Load
V
EXT
V
I
f
i
t
W
t
r
, t
f
C
L
R
L
t
PHZ
, t
PZH
t
PLZ
, t
PZL
t
PLH
, t
PHL
2.7 V
10 MHz
500 ns
2.5 ns
50 pF
500
GND
6 V
open
74L
VTN16244B
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 201
2. All rights rese
rved.
Product data sheet
Rev
. 5 — 2 April 2012
1
1 of 16
NXP Semiconductors
74L
VTN16244B
3.3 V 16-bit buffer/driver
; 3-st
ate
12. Package
outline
Fig 8.
Package outlin
e SOT362-
1 (TSSOP48)
UNIT
A
1
A
2
A
3
b
p
cD
(1)
E
(2)
eH
E
LL
p
QZ
y
w
v
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
0.15
0.05
0.2
0.1
8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1
99-12-27
03-02-19
w
M
θ
A
A
1
A
2
D
L
p
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
12
4
48
25
y
pin 1 index
b
H
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
0.5
1
0.25
8.3
7.9
0.50
0.35
0.8
0.4
0.08
0.8
0.4
p
E
v
M
A
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P17
74LVTN16244BDGG,11
Mfr. #:
Buy 74LVTN16244BDGG,11
Manufacturer:
Nexperia
Description:
Buffers & Line Drivers BiCMOS 4CH NONINVERT
Lifecycle:
New from this manufacturer.
Delivery:
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EMS
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