14
FN7317.2
February 4, 2005
500kHz when reasonable currents are being drawn. (For
lower load currents, the gain and hence bandwidth
progressively decreases.) This means the active
transconductance is:
This high transconductance indicates why it is important to
have a low ESR capacitor.
If:
• ESR * 3.14 > 1
then the capacitor will not force the gain to roll off below
unity, and subsequent poles can affect stability. The
recommended capacitor has an ESR of 10mΩ, but to this
must be added the resistance of the board trace between the
capacitor and the V
COM
pin, where the sense connection is
made internally - therefore this should be kept short. Also
ground resistance between the capacitor and the base of R
2
must be kept to a minimum. These constraints should be
considered when laying out the PCB.
If the capacitor is increased above 1µF, stability is generally
improved and short pulses of current will cause a smaller
“perturbation” on the V
COM
voltage. The speed of response
of the amplifier is however degraded as its bandwidth is
decreased. At capacitor values around 10µF, a subtle
interaction with internal DC gain boost circuitry will decrease
the phase margin and may give rise to some overshoot in
the response. The amplifier will remain stable, though.
Response to High Current Spikes
The V
COM
amplifier's output current is limited to 180mA.
This limit level, which is roughly the same for sourcing and
sinking, is included to maintain reliable operation of the part.
It does not necessarily prevent a large temperature rise if the
current is maintained. (In this case the whole chip may be
shut down by the thermal trip to protect functionality.) If the
display occasionally demands current pulses higher than
this limit, the reservoir capacitor will provide the excess and
the amplifier will top the reservoir capacitor back up once the
pulse has stopped. This will happen on the µs time scale in
practical systems and for pulses 2 or 3 times the current
limit, the V
COM
voltage will have settled again before the
next line is processed.
Power-Up Sequencing
With the components shown in the application diagram the
on-chip power-up sequencing operates as follows.
When the EN pin is taken to logic 1, the following sequence
is followed by on-chip functions:
1. The boost circuit and negative charge pumps are
enabled. V
BOOST
rises at a rate set by the boost load
capacitor, the external load, and the boost’s current limit
(controlled by the SS pin input.) Similarly, V
OFF
falls in
voltage determined by the load capacitor, the V
OFF
load,
and the current capability of these negative charge
pumps (which is rising as V
BOOST
and hence V
DDN
rises.)
2. When V
BOOST
reaches a voltage such that V(FBB)>
1.13V and V
OFF
first reaches its required regulation
voltage, the V
COM
regulator is enabled and V
COM
rises
at a rate determined by the V
COM
load capacitor, the load
on V
COM
, and the current limit of the V
COM
amplifier.
3. When V
COM
rises to within 100mV of V(INC), an internal
delay circuit triggers and, for V
DDP
= 12V, a default delay
of approximately 3.5ms is introduced before the positive
charge pump is then enabled. This delay can be
increased externally by connecting a capacitor between
DP and V
SSP
. A 1nF capacitor will typically increase the
delay before V
ON
becomes enabled to 80ms.
The enabled states of the on-chip functions become
independent of V
BOOST
, V
OFF
, V
COM
, and V
ON
once each
is triggered. The chip may be reset by forcing EN to logic 0
and allowing sufficient time for the various supplies to
discharge sufficiently before taking EN to 1 again.
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that die temperature exceeds
the thermal trip point, the device will shut down and disable
itself. The upper and lower trip points are typically set to
130°C and 90°C respectively.
PCB Layout Guidelines
Careful layout is critical in the successful operation of the
application. The following layout guidelines are
recommended to achieve optimum performance.
1. V
REF
and V
DDB
bypass capacitors should be placed next
to the pins.
2. Place the boost converter diode and inductor close to the
LX pins.
3. Place the boost converter output capacitor close to the
PGND pins.
4. Locate feedback dividers close to their respected
feedback pins to avoid switching noise coupling into the
high impedance node.
5. Place the charge pump feedback resistor network after
the diode and output capacitor node to avoid switching
noise.
6. All low-side feedback resistors should be connected
directly to V
SSB
. V
SSB
should be connected to the power
ground at one point only.
A demo board is available to illustrate the proper layout
implementation.
EL7584
