IDT
®
19 Output Differential Buffer for PCIe Gen2 and QPI 1607C—04/19/11
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
6
Electrical Characteristics - Input/Supply/Common Parameters
TA = T
COM;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Ambient Operating
Temperature
T
COM
Commmercial range 0 70 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2V
DD
+ 0.3 V 1
Input Low Voltage V
IL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
GND
- 0.3 0.8 V 1
Low Threshold Input-
High Voltage
V
IH_FS
3.3 V +/-5%, Applies to 100M_133M#_LV pin 0.7 V
DD
+ 0.3 V 1
Low Threshold Input-
Low Voltage
V
IL_FS
3.3 V +/-5%, Applies to 100M_133M#_LV pin V
SS
- 0.3 0.35 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
F
ib
V
DD
= 3.3 V, Bypass mode 33 400 MHz 2
F
i
ll
V
DD
= 3.3 V, 100MHz PLL mode 90 100.00 110 MHz 2
F
i
ll
V
DD
= 3.3 V, 133.33MHz PLL mode 120 133.33 147 MHz 2
Pin Inductance L
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
I NDI F_I N
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1.8 ms 1,2
Input SS Modulation
Frequency
f
MODIN
Allowable Frequency
(Triangular Modulation)
30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
412clocks1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
Fall time of control inputs 5 ns 1,2
Trise t
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 100 kHz 1,5
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
5
The differential in
ut clock must be runnin
for the SMBus to be active
Input Current
3
Time from deassertion until out
uts are >200 mV
4
DIF_IN input
Capacitance
Input Frequency