FST3126DR2G

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4
DC ELECTRICAL CHARACTERISTICS
V
CC
T
A
= −55_C to +125_C
Symbol Parameter Conditions (V) Min Typ* Max Unit
V
IK
Clamp Diode Resistance I
IN
= *18mA 4.5 *1.2 V
V
IH
High−Level Input Voltage 4.0 to 5.5 2.0 V
V
IL
Low−Level Input Voltage 4.0 to 5.5 0.8 V
I
I
Input Leakage Current 0 v V
IN
v 5.5 V 5.5 $1.0
mA
I
OZ
OFF−STATE Leakage Current 0 v A, B v V
CC
5.5 $1.0
mA
R
ON
Switch On Resistance (Note 6) V
IN
= 0 V, I
IN
= 64 mA 4.5 4 7
W
V
IN
= 0 V, I
IN
= 30 mA 4.5 4 7
V
IN
= 2.4 V, I
IN
= 15 mA 4.5 8 15
V
IN
= 2.4 V, I
IN
= 15 mA 4.0 11 20
I
CC
Quiescent Supply Current V
IN
= V
CC
or GND, I
OUT
= 0 5.5 3
mA
DI
CC
Increase In I
CC
per Input One input at 3.4 V, Other inputs at V
CC
or GND 5.5 2.5 mA
*Typical values are at V
CC
= 5.0 V and T
A
= 25_C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch.
AC ELECTRICAL CHARACTERISTICS
Limits
T
A
= −55_C to +125_C
V
CC
= 4.5 to 5.5 V V
CC
= 4.0 V
Symbol Parameter Conditions Figures Min Max Min Max Unit
t
PHL
,
t
PLH
Prop Delay Bus to Bus
(Note 7)
V
I
= OPEN 3 and 4 0.25 0.25 ns
t
PZH
,
t
PZL
Output Enable Time V
I
= 7 V for t
PZL
V
I
= OPEN for t
PZH
3 and 4 1.0 4.5 5.0 ns
t
PHZ
,
t
PLZ
Output Disable Time V
I
= 7 V for t
PLZ
V
I
= OPEN for t
PHZ
3 and 4 1.5 5.7 6.2 ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol Parameter Conditions Typ Max Unit
C
IN
Control Pin Input Capacitance V
CC
= 5.0 V 3 pF
C
I/O
Input/Output Capacitance V
CC
= 5.0 V, OE = 0 V 5 pF
8. T
A
= )25_C, f = 1 MHz, Capacitance is characterized but not tested.
FST3126
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5
V
I
V
OL
V
OL
+ 0.3 V
t
PLH
t
PLH
V
OL
V
OH
V
OH
− 0.3 V
t
PHZL
t
f
= 2.5 nS
90 %
1.5 V
10 %10 %
1.5 V
90 %
t
f
= 2.5 nS
t
PZL
t
PZL
OUTPUT
1.5 V
OUTPUT
1.5 V
GND
3.0 V
t
PZH
ENABLE
INPUT
t
f
= 2.5 nS
90 %
1.5 V1.5 V
90 %
10 % 10 %
1.5 V 1.5 V
V
OH
GND
3.0 V
SWITCH
INPUT
t
f
= 2.5 nS
C
L
*
FROM
OUTPUT
UNDER
TEST
Figure 3. AC Test Circuit
Figure 4. Propagation Delays
AC Loading and Waveforms
NOTES:
1. Input driven by 50 W source terminated in 50 W.
2. CL includes load and stray capacitance.
*C
L
= 50 pF
500 W
500 W
Figure 5. Enable/Disable Delays
OUTPUT
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6
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE L
6.50
14X
0.58
14X
1.18
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
H
14
8
71
M
0.25 B
M
C
h
X 45
SEATING
PLANE
A1
A
M
_
S
A
M
0.25 B
S
C
b
13X
B
A
E
D
e
DETAIL A
L
A3
DETAIL A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
A 1.35 1.75 0.054 0.068
b 0.35 0.49 0.014 0.019
L 0.40 1.25 0.016 0.049
e 1.27 BSC 0.050 BSC
A3 0.19 0.25 0.008 0.010
A1 0.10 0.25 0.004 0.010
M 0 7 0 7
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
__ __
0.10

FST3126DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Digital Bus Switch ICs 4-bit Bus Switch
Lifecycle:
New from this manufacturer.
Delivery:
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