LTC3676/LTC3676-1
19
3676fe
For more information www.linear.com/LTC3676
OPERATION
Table 6. Buck3 Control Command Register
COMMAND
REGISTER[BIT] VALUE SETTING
BUCK3[0] 0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
BUCK3[1] 0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
BUCK3[2] 0*
1
Switching Frequency 2.25MHz
Switching Frequency 1.125MHz
BUCK3[3] 0*
1
Clock Phase 1
Clock Phase 2
BUCK3[4] 0*
1
Enable at Any Output V
oltage
Enable Only if Output Voltage Is <300mV
BUCK3[6:5] 00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
For
ced Continuous Mode
BUCK3[7] 0*
1
Buck3 Disabled if EN_B3 Pin Is Low
Buck3 Enabled
*denotes default power-on value.
Table 7. Buck4 Control Command Register
COMMAND
REGISTER[BIT] VALUE SETTING
BUCK4[0] 0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
BUCK4[1] 0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
BUCK4[2] 0*
1
Switching Frequency 2.25MHz
Switching Frequency 1.125MHz
BUCK4[3] 0*
1
Clock Phase 1
Clock Phase 2
BUCK4[4] 0*
1
Enable at Any Output V
oltage
Enable Only if Output Voltage Is <300mV
BUCK4[6:5] 00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
For
ced Continuous Mode
BUCK4[7] 0*
1
Buck4 Disabled if EN_B4 Pin Is Low
Buck4 Enabled
*denotes default power-on value.
SLEWING DAC REFERENCE OPERATION
Each LTC3676 step-down switching regulators error am-
plifier reference
voltage is supplied by a 5-bit DAC with
an output voltage range of 412.5mV to 800mV in 12.5mV
steps. One of two 5-bit codes stored in I
2
C command
registers is selected for input to the DAC. When a change
in code is detected by the DAC control circuits, the output
of the DAC is slewed at 3.5mV/µs to the new value.
Dynamic Voltage Scaling
Table 8 shows the command registers used to control
dynamic voltage scaling (DVS) of the step-down switching
regulators input reference DAC. The command register
bits DVB1A[4:0] and DVB1B[4:0] store two 5-bit inputs
to the DAC reference for Buck1. The bit stored in com
-
mand register
DVB1A[5] selects either the 5 bits stored
in DVB1A[4:0] or DVB1B[4:0] DAC as input to the DAC
reference. Buck2, Buck3, and Buck4 operate the same
way using their assigned “A” and “B” command registers
shown in Table 8. When the DAC detects a change in its
input code it automatically slews to the new value at a rate
of 3.5mV/µs. A DVS can be initiated using the I
2
C select
bit or using the VSTB pin.
The LTC3676 VSTB pin HIGH selects the 5 bits stored in
all four DVBx “
B” registers. This facilitates a simultaneous
DAC slew between the values in the “A” registers and the
values in the “B” registers. The VSTB pin is logically ORed
with the I
2
C command register bit. If the I
2
C select bit is
already set high, the “B” registers are already selected and
VSTB will have no effect. If no change in output is desired
using the VSTB pin, set the value in the “A” register equal
to the value in the “B”.
Command register bits DVB1B[5], DVB2B[5], DVB3B[5],
and DVB4B[5] control whether the PGOOD status pin is
pulled low while the DAC output is slewing. The default
command register setting is to pull PGOOD pin low dur
-
ing DAC slew. During the DVS, PGOOD will be held low
for just the duration of the DVS and the PGSTAT register
is not affected.
Figure 5. Dynamic Voltage Scaling
V
OUT
200mV/DIV
PGOOD
5V/DIV
VSTB
5V/DIV
100µs/DIV
3676 F05