RT8010/A
13
DS8010/A-10 February 2015 www.richtek.com
©
Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
(ESR), where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used
by the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability problem.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8010/A.
For the main current paths as indicated in bold lines in
Figure 6, keep their traces short and wide.
Put the input capacitor as close as possible to the device
pins (VIN and GND).
LX node is with high frequency voltage swing and should
be kept small area. Keep analog components away from
LX node to prevent stray capacitive noise pick-up.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main switch
and the synchronous switch. Thus, the series resistance
looking into the LX pin is a function of both top and bottom
MOSFET R
DS(ON)
and the Duty Cycle (DC) as follows :
R
SW
= R
DS(ON)TOP
x DC + R
DS(ON)BOT
x (1 − DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature, T
A
is the ambient temperature and the θ
JA
is
the junction to ambient thermal resistance.
For recommended operating conditions specification,
where T
J(MAX)
is the maximum junction temperature of the
die and T
A
is the maximum ambient temperature. The
junction to ambient thermal resistance θ
JA
is layout
dependent. For WDFN-6L 2x2 packages, the thermal
resistance θ
JA
is 120°C/W on the standard JEDEC 51-7
four layers thermal test board.
The maximum power dissipation at T
A
= 25°C can be
calculated by following formula :
P
D(MAX)
= (125°C − 25°C) / 120°C/W = 0.833W for
WDFN-6L 2x2 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance θ
JA
.
The Figure 5 of derating curves allows the designer to
see the effect of rising ambient temperature on the
maximum power allowed.
Figure 5. Derating Curve of Maximum Power Dissipation
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four Layers PCB
WDFN-6L 2x2
WQFN-16L 3x3
