Semiconductor Components Industries, LLC, 2003
September, 2003 − Rev. 0
1 Publication Order Number:
MC100LVEL34/D
MC100LVEL34
3.3VECL ÷2, ÷4, ÷8 Clock
Generation Chip
The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The V
BB
pin, an internally
generated voltage supply, is available to this device only. For
single−ended input conditions, the unused differential input is
connected to V
BB
as a switching reference voltage. V
BB
may also
rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a
0.01 F capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
BB
should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon start−up, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple LVEL34s in a system.
• 50 ps Typical Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• 1.5 GHz Toggle Frequency
• The 100 Series Contains Temperature Compensation.
• PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −3.8 V
• Open Input Default State
• LVDS Input Compatible
SO−16
D SUFFIX
CASE 751B
1
16
MARKING
DIAGRAMS*
A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
Device Package Shipping
ORDERING INFORMATION
MC100LVEL34D SO−16 48 Units/Rail
MC100LVEL34DR2 SO−16 2500 Units/Reel
MC100LVEL34DT TSSOP−16 96 Units/Rail
MC100LVEL34DTR2 TSSOP−16
2500 Units/Reel
1
16
100LVEL34
AWLYWW
1
16
TSSOP−16
DT SUFFIX
CASE 948F
VL34
ALYW
100
1
16
*For additional information, refer to Application Note
AND8002/D
http://onsemi.com
