7©2016 Integrated Device Technology, Inc. Revison B, February 8, 2016
850S1201 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Offset Frequency (Hz)
SSB Phase Noise dBc/Hz
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.35ps (typical)
8©2016 Integrated Device Technology, Inc. Revison B, February 8, 2016
850S1201 Datasheet
Parameter Measurement Information
3.3V Output Load AC Test Circuit
Part-to-Part Skew
Output Duty Cycle/Pulse Width/Period
2.5V Output Load AC Test Circuit
Input Skew
SCOPE
Qx
GND
V
DD
1.65V±5%
-1.65V±5%
t
sk(pp)
V
DD
2
V
DD
2
Part 1
Part 2
Qx
Qy
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
Q
SCOPE
Qx
GND
V
DD
1.25V±5%
-1.25V±5%
t
PD1
t
PD2
tsk(i) = t
PD2
– t
PD1
tsk (i)
CLK2
Q
CLK1
9©2016 Integrated Device Technology, Inc. Revison B, February 8, 2016
850S1201 Datasheet
Parameter Measurement Information, continued
MUX Isolation
Propagation Delay
Output Rise/Fall Time
Recommendations for Unused Input Pins
Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
CLKx
(static) CLKy
CLK_SELy
Q
Spectrum
MUX
_ISOL
CLKx CLKy
Q
CLK0:
CLK11
Q

850S1201BGILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution LVCMOS 12:1 MUX
Lifecycle:
New from this manufacturer.
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