DATASHEET
LOW PHASE NOISE CLOCK MULTIPLIER ICS601-01
IDT™ / ICS™
LOW PHASE NOISE CLOCK MULTIPLIER 1
ICS601-01 REV M 102709
Description
The ICS601-01 is a low-cost, low phase noise,
high-performance clock synthesizer for applications
which require low phase noise and low jitter. It is IDT’s
lowest phase noise multiplier, and also the lowest
CMOS part in the industry. Using IDT’s patented
analog and digital Phase-Locked Loop (PLL)
techniques, the chip accepts a 10 - 27 MHz crystal or
clock input, and produces output clocks up to 156 MHz
at 3.3 V.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require definted input to output
timing, use the ICS670-01.
Features
• Packaged in 16-pin SOIC or TSSOP
• Available in Pb (lead) free package
• Uses fundamental 10 - 27 MHz crystal or clock
• Patented PLL with the lowest phase noise
• Output clocks up to 156 MHz at 3.3 V
• Low phase noise: -132 dBc/Hz at 10 kHz
• Low jitter - 18 ps one sigma typ.
• Full swing CMOS outputs with 25 mA drive capability
at TTL levels
• Advanced, low power, sub-micron CMOS process
• Industrial temperature range available
• Operating voltage of 3.3V or 5V
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
ROM Based
Multipliers
VCO
Divide
X1/ICLK
X2
Crystal or
clock input
Crystal
Oscillator
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
S3:0
GND
3
4
VDD
3
CLK
REFOUT
REFEN
OE