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74LVC02APW,112

P1-P3P4-P6P7-P9P10-P12P13-P15
74LVC02A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 16 November 2011 3 of 14
NXP Semiconductors
74LVC02A
Quad 2-input NOR gate
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO14 packages: above 70 C derate linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.
Table 2. Pin description
Symbol Pin Description
1Y to 4Y 1, 4, 10, 13 data output
1A to 4A 2, 5, 8, 11 data input
1B to 4B 3, 6, 9,12 data input
GND 7 ground (0 V)
V
CC
14 supply voltage
Table 3. Function table
[1]
Input nA Input nB Output nY
LLH
XHL
HXL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +6.5 V
I
IK
input clamping current V
I
< 0 V 50 - mA
V
I
input voltage
[1]
0.5 +6.5 V
I
OK
output clamping current V
O
> V
CC
or V
O
< 0 V - 50 mA
V
O
output voltage output in HIGH or LOW-state
[2]
0.5 V
CC
+ 0.5 V
I
O
output current V
O
= 0 V to V
CC
- 50 mA
I
CC
supply current - 100 mA
I
GND
ground current 100 - mA
P
tot
total power dissipation T
amb
= 40 C to +125 C
[3]
- 500 mW
T
stg
storage temperature 65 +150 C
74LVC02A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 16 November 2011 4 of 14
NXP Semiconductors
74LVC02A
Quad 2-input NOR gate
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage 1.65 - 3.6 V
functional 1.2 - - V
V
I
input voltage 0 - 5.5 V
V
O
output voltage output HIGH or LOW state 0 - V
CC
V
T
amb
ambient temperature 40 - +125 C
t/V input transition rise and fall rate V
CC
= 1.65 V to 2.7 V 0 - 20 ns/V
V
CC
= 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
V
IH
HIGH-level
input voltage
V
CC
= 1.2 V 1.08 - - 1.08 - V
V
CC
= 1.65 V to 1.95 V 0.65  V
CC
- - 0.65 V
CC
-V
V
CC
= 2.3 V to 2.7 V 1.7 - - 1.7 - V
V
CC
= 2.7 V to 3.6 V 2.0 - - 2.0 - V
V
IL
LOW-level
input voltage
V
CC
= 1.2 V - - 0.12 - 0.12 V
V
CC
= 1.65 V to 1.95 V - - 0.35 V
CC
-0.35 V
CC
V
V
CC
= 2.3 V to 2.7 V - - 0.7 - 0.7 V
V
CC
= 2.7 V to 3.6 V - - 0.8 - 0.8 V
V
OH
HIGH-level
output
voltage
V
I
=V
IH
or V
IL
I
O
= 100 A;
V
CC
=1.65Vto3.6V
V
CC
0.2 - - V
CC
0.3 - V
I
O
= 4mA; V
CC
= 1.65 V 1.2 - - 1.05 - V
I
O
= 8mA; V
CC
= 2.3 V 1.8 - - 1.65 - V
I
O
= 12 mA; V
CC
= 2.7 V 2.2 - - 2.05 - V
I
O
= 18 mA; V
CC
= 3.0 V 2.4 - - 2.25 - V
I
O
= 24 mA; V
CC
= 3.0 V 2.2 - - 2.0 - V
V
OL
LOW-level
output
voltage
V
I
=V
IH
or V
IL
I
O
= 100 A;
V
CC
= 1.65 V to 3.6 V
- - 0.2 - 0.3 V
I
O
=4mA; V
CC
= 1.65 V - - 0.45 - 0.65 V
I
O
=8mA; V
CC
= 2.3 V - - 0.6 - 0.8 V
I
O
=12mA; V
CC
= 2.7 V - - 0.4 - 0.6 V
I
O
=24mA; V
CC
= 3.0 V - - 0.55 - 0.8 V
I
I
input leakage
current
V
CC
= 3.6 V; V
I
=5.5VorGND - 0.1 5- 20 A
74LVC02A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 16 November 2011 5 of 14
NXP Semiconductors
74LVC02A
Quad 2-input NOR gate
[1] All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
=25C.
10. Dynamic characteristics
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
(C
L
V
CC
2
f
o
) = sum of the outputs
I
CC
supply
current
V
CC
= 3.6 V; V
I
=V
CC
or GND;
I
O
=0A
-0.110-40A
I
CC
additional
supply
current
per input pin;
V
CC
= 2.7 V to 3.6 V;
V
I
=V
CC
0.6 V; I
O
=0A
- 5 500 - 5000 A
C
I
input
capacitance
V
CC
= 0 V to 3.6 V;
V
I
=GNDtoV
CC
-4.0---pF
Table 6. Static characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7
.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation delay nA, nB to nY; see Figure 6
[2]
V
CC
=1.2V - 14 - - - ns
V
CC
= 1.65 V to 1.95 V 0.5 4.0 8.6 0.5 10.1 ns
V
CC
= 2.3 V to 2.7 V 1.0 2.4 4.9 1.0 5.7 ns
V
CC
= 2.7 V 1.0 2.5 5.1 1.0 6.5 ns
V
CC
= 3.0 V to 3.6 V 1.0 2.2 4.4 1.0 5.5 ns
t
sk(o)
output skew time V
CC
= 3.0 V to 3.6 V
[3]
- - 1.0 - 1.5 ns
C
PD
power dissipation
capacitance
per gate; V
I
=GNDtoV
CC
[4]
V
CC
= 1.65 V to 1.95 V - 2.5 - - - pF
V
CC
= 2.3 V to 2.7 V - 5.7 - - - pF
V
CC
= 3.0 V to 3.6 V - 8.5 - - - pF
P1-P3P4-P6P7-P9P10-P12P13-P15

74LVC02APW,112

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Buy 74LVC02APW,112
Manufacturer:
Nexperia
Description:
Logic Gates 3.3V QUAD 2-INPUT
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