AS1701-T Datasheet AS1706-T, AS1706, AS1701 | P10-P12

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AS1701, AS1706

Datasheet - Detailed Description

8 Detailed Description

The AS1701/AS1706 bridged audio power-amplifiers can deliver 1.6W into 4Ω while operating from a single 2.7 to 5.5V supply. The devices

consist of two high-output-current operational amplifiers configured as a bridge-tied load (BTL) amplifier as shown in Figure 29.

Figure 29. AS1701 Typical Configuration Block Diagram

The gain of the devices is set by the closed-loop gain of the input operational amplifier. As shown in Figure 29, the output of the first amplifier

serves as the input to the second amplifier, which is configured as an inverting unity-gain follower in both devices. This results in two outputs,

identical in magnitude, and 180° out-of-phase.

Bias

The devices operate from a single 2.7 to 5.5V supply and contain an internally generated, common-mode bias voltage of:

DD/2 (EQ 1)

referenced to ground. Bias provides click-and-pop suppression and sets the DC bias level for the audio outputs. For selection of the value for the

bias bypass capacitor (C

BIAS), see Bias Bypass Capacitor on page 13. Pin BIAS is internally connected to the non-inverting input of one ampli-

fier, and should be connected to the non-inverting input of the other amplifier for proper signal biasing (see Figure 29).

Shutdown

The integrated 100nA, low-power shutdown circuitry reduces quiescent current consumption. As shutdown commences, the bias circuitry is

automatically disabled, the device outputs go high impedance, and bias is driven to GND.

Note: Connect SHDN to GND for the AS1701 (active-high); connect SHDN to V

DD for the AS1706 (active-low).

Current Limit

The AS1701/AS1706 current limit circuitry protects the device during output short-circuit and overload conditions. When both amplifier outputs

are shorted to either V

DD or GND, the short-circuit protection is enabled and the amplifier enters a pulsing mode, reducing the average output

current to a safe level. The amplifier remains in this mode until the short-circuit or overload condition is corrected.

40kΩ

4 or 8Ω

40kΩ

50kΩ

DD/2

Bias

20kΩ

20kΩ RF

VDD

–

CIN

0.33µF

Audio

Input

S0.1µF

Av = -1

0.1 to

1.0µF

AS1701

IN-

IN+

BIAS

SHDN

GND

OUT-

OUT+

VDD

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AS1701, AS1706

Datasheet - Application Information

9 Application Information

BTL Amplifier

The AS1701/AS1706 are designed to drive loads differentially in a bridge-tied load (BTL) configuration.

Figure 30. Bridge-Tied Load Configuration

Driving the load differentially doubles the output voltage (illustrated in Figure 30) compared to a single-ended amplifier under similar conditions.

Thus, the differential gain of the device is twice the closed-loop gain of the input amplifier. The effective gain is calculated by:

Substituting 2 x V

OUT(P-P) into (EQ 3) and (EQ 4) yields four times the output power due to doubling of the output voltage.

Since the differential outputs are biased at mid-supply, there is no net DC voltage across the load, eliminating the need for the large, expensive,

performance degrading DC-blocking capacitors required by single-ended amplifiers.

Power Dissipation and Heat Sinking

Normally, the devices dissipate a significant amount of power. The maximum power dissipation is given in Table 2 as Continuous Power Dissipa-

tion, or it can be calculated by:

where T

J(MAX) is +150°C, TAMB (see Table 2) is the ambient temperature, and ΘJA is the reciprocal of the derating factor in °C/W.

The increased power delivered by a BTL configuration normally results in increased internal power dissipation versus a single-ended configura-

tion. The maximum internal power dissipation for a given V

DD and load is calculated by:

If the internal power dissipation exceeds the maximum allowed for a given package, power dissipation can be reduced by increasing the ground

plane heat-sinking capabilities and increasing the size of the traces to the device (see Layout and Grounding Considerations on page 14). Addi-

tionally, reducing V

DD, increasing load impedance, and decreasing ambient temperature can reduce device power dissipation.

-1

VOUT(P-P)

2 x VOUT(P-P)

AVD = 2 x

RIN

(EQ 2)

VRMS =

2 2

(EQ 3)

VOUT(P-P)

POUT =

(EQ 4)

VRMS

PDISSPKF(MAX) =

(EQ 5)

TJ(MAX) -TA

PDISSPKF(MAX) =

(EQ 6)

2VDD

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AS1701, AS1706

Datasheet - Application Information

The integrated thermal-overload protection circuitry limits the total device power dissipation. Note that if the junction temperature is ≥ +145°C,

the integrated thermal-overload protection circuitry will disable the amplifier output stage. If the junction temperature is reduced by 9ºC, the

amplifiers will be re-enabled.

Note: A pulsing output under continuous thermal overload results as the device heats and cools.

Efficiency

Efficiency of the AS1701/AS1706 is calculated by taking the ratio of the power delivered to the load, to the power consumed from the power sup-

ply. Output power is calculated by:

where V

PEAK is half the peak-to-peak output voltage. In BTL amplifier configurations, the supply current waveform is a full-wave rectified sinu-

soid with the magnitude proportional to the peak output voltage and load.

Calculate the supply current and power drawn from the power supply by:

The efficiency of the AS1701/AS1706 is:

Component Selection

Gain-Setting Resistors

External feedback resistors RF and RIN (see Figure 1 on page 1) set the gain of the device as:

Optimum output offset is achieved when R

F = 20kΩ. Device gain can be varied by changing the value of RIN.

If used in a high-gain configuration (greater than 8V/V), a feedback capacitor may be required to maintain stability (see Figure 1 on page 1). C

and R

F limit the bandwidth of the device, preventing high-frequency oscillations.

Note: Ensure that the pole created by C

F and RF is not within the frequency band of interest.

Input Filter

Input capacitor CIN (if used), in conjunction with RIN, forms a high-pass filter that removes the DC bias from an incoming signal. CIN allows the

amplifier to bias the signal to an optimum DC level. Assuming zero source impedance, the -3dB point of the high-pass filter is given by:

POUT =

(EQ 7)

VPEAK

IDD =

πRL

(EQ 8)

2VPEAK

PIN = VDD

πRL

(EQ 9)

2VPEAK

η =

(EQ 10)

RIN

POUT

= π

POUTRL

AVD = 2 x

(EQ 11)

f-3dB =

(EQ 12)

2πRINCIN

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