LTC4007-1
10
40071fa
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Table 1. Truth Table for LTC4007-1 Operation (Supplemental)
NUMBER
FROM
STATE
TO
STATE MODE DCIN
BATTERY
VOLTAGE
PRESENT
C/10
LATCH
NEXT
C/10
LATCH
MAX
BATTERY
CURRENT ACP
TIMER
STATE CHG
1 Any MSD Shut Down by Low
Adapter Voltage
<B
AT 0 OFF LOW Reset HIGH
2 MSD SD Charger Shutdown >BAT 0 OFF HIGH Reset HIGH
3 SD,
CONDITION,
CHARGE
SD Shut Down by
Undervoltage Lockout
>BAT
and
<UVL
OFF HIGH Reset HIGH*
4 SD CONDITION Start Conditioning a
Depleted Battery
>BAT <3.25V/Cell 10%
Programmed
Current
HIGH LOW
5 CONDITION CONDITION Input Current Limited
Condition Charging
>BAT <3.25V/Cell <10%
Programmed
Current (Note 2)
HIGH Running LOW
6 CONDITION CONDITION Conditioning a
Depleted Battery
>B
AT <3.25V/Cell 10%
Programmed
Current
HIGH Running LOW
7 CONDITION CONDITION Timer Defeated (Low
Battery Conditioning Still
Functional)
>BAT <3.25V/Cell 10%
Programmed
Current
HIGH Ignored Forced
LOW
8 CONDITION SD Charger Paused Due to
Thermistor Out of Range
>BAT <3.25V/Cell OFF HIGH Paused LOW
(Faulted)
9 CONDITION SD Timeout in
CONDITION Mode
>B
AT <3.25V/Cell OFF HIGH >T/4 HIGH
(Faulted)
10 CONDITION SD Shut Down by
ACP/SHDN Pin
>B
AT <3.25V/Cell 0 OFF Forced
LOW
Reset HIGH
11 CONDITION CHARGE Start Normal Charging >BAT >3.25V/Cell Programmed
Current
HIGH Running
12 CHARGE CHARGE Timer Defeated (Low
Battery Conditioning Still
Functional)
>BAT >3.25V/Cell Programmed
Current
HIGH Ignored Forced
LOW
13 CHARGE CHARGE Top-Off Charging >BAT >3.25V/Cell 0 Programmed
Current
HIGH Running LOW
14 CHARGE CHARGE C/10 Latch is SET
when Battery Current
Is Less than 10% of
Programmed Current
>BAT >3.25V/Cell 1 Programmed
Current
HIGH Reset 25µA
15 CHARGE CHARGE Top-Off Charging >BAT >3.25V/Cell 1 Programmed
Current
HIGH Running 25µA
16 CHARGE CHARGE Input Current
Limited Charging
>
B
AT >3.25V/Cell <Programmed
Current (Note 2)
HIGH
17 CHARGE SD Charger Paused Due to
Thermistor Out of Range
>BAT >3.25V/Cell OFF HIGH Paused LOW or
25µA
(Faulted)
18 CHARGE SD Shut Down by
ACP/SHDN Pin
>
B
AT >3.25V/Cell 0 OFF Forced
LOW
Reset HIGH
19 CHARGE SD Terminated by Low-
Battery Fault (Note 1)
>BAT <3.25V/Cell 0 OFF HIGH >T/4 then
Reset
HIGH
(Faulted)
20 CHARGE SD Terminates After T/4 >BAT V
FLOAT
1 OFF HIGH >T/4 then
Reset
HIGH
21 CHARGE SD Terminates After T >BAT V
FLOAT
* 0 OFF HIGH >T then
Reset
HIGH
*Most probable condition
Note 1: If a depleted battery is inserted while the charger is in this state,
the charger must be reset to initiate charging.
Note 2: See section on “Adapter Limiting”.
Note 3: Blank fields indicate no change, not considered, or other states
impact value.
Note 4: Battery voltage thresholds do not include comparator hysterisis.
Thresholds specify the VLH value.
operaTion
LTC4007-1
11
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operaTion
LTC4007-1: State Diagram
40071 TBL01
MASTER
SHUTDOWN
SHUTDOWN
ANY
1
2
4
11
12, 13, 14, 15, 16
3, 17, 18,
19, 20, 21
3, 8,
9, 10
5, 6, 7
CONDITION
CHARGE
The gate of the input FET is driven to a voltage sufficient
to keep a low forward voltage drop from drain to source.
If the voltage between DCIN and CLN drops to less than
25mV, the input FET is turned off slowly. If the voltage
between DCIN and CLN is ever less than –25mV, then
the input FET is turned off in less than 10µs to prevent
significant reverse current from flowing in the input FET. In
this condition, the ACP pin is driven low and the charger
is disabled.
Battery Charger Controller
The LTC4007-1 charger controller uses a constant off-
time, current mode step-down architecture. During normal
operation, the top MOSFET is turned on each cycle when
the oscillator sets the SR latch and turned off when the
main current comparator I
CMP
resets the SR latch. While
the top MOSFET is off, the bottom MOSFET is turned on
until either the inductor current trips the current compara
-
tor I
REV
or the beginning of the next cycle. The oscillator
uses the equation:
t
VV
Vf
OFF
DCIN BAT
DCIN OSC
=
to set the bottom MOSFET on time. The result is a nearly
constant switching frequency over a wide input/output
voltage range. This activity is diagrammed in Figure 1.
The peak inductor current, at which I
CMP
resets the SR
latch, is controlled by the voltage on ITH. ITH is in turn
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative cur
-
rent. Error amp CA2 compares this current against the
TGATE
OFF
ON
BGATE
INDUCTOR
CURRENT
t
OFF
TRIP POINT SET BY ITH VOLTAGE
ON
OFF
40071 F01
Figure 1
LTC4007-1
12
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operaTion
desired current programmed by RPROG at the PROG pin
and adjusts ITH until:
V
R
VV Ak
k
REF
PROG
CSP BAT
=
Ω
Ω
–.•.
.
11 67 301
301
therefore,
I
V
R
A
k
R
CHARGE MAX
REF
PROG SENSE
()
–.
.
Ω
11 67
301
The voltage at BAT is divided down by an internal resis-
tor divider and is used by error amp EA to decrease ITH
if the divider voltage is above the 1.19V
reference. When
the charging current begins to decrease, the voltage at
PROG will decrease in direct proportion. The voltage at
PROG is then given by:
VI RAk
R
k
PROG CHARGE SENSE
PROG
=+μΩ
()
Ω
•.•.
.
11 67 301
301
V
PROG
is plotted in Figure 2.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter to a preset level (100mV/
R
CL
). At input current limit, CL1 will decrease the ITH volt-
age, thereby reducing charging current. The I
CL
indicator
output will go low when this condition is detected and the
FLAG indicator will be inhibited if it is not already LOW.
If the charging current decreases below 10% to 15%
of programmed current while engaged in input current
limiting, BGATE will be forced low to prevent the charger
from discharging the battery. Audible noise can occur in
this mode of operation.
An overvoltage comparator guards against voltage transient
overshoots (>7% of programmed value). In this case, both
MOSFETs are turned off until the overvoltage condition
is cleared. This feature is useful for batteries which “load
dump” themselves by opening their protection switch
to perform functions such as calibration or pulse mode
charging.
PWM Watchdog Timer
There is a watchdog timer that observes the activity on
the BGATE and TGATE pins. If TGATE stops switching for
more than 40µs, the watchdog activates and turns off the
top MOSFET for about 400ns. The watchdog engages to
prevent very low frequency operation in dropouta po
-
tential source of audible noise when using ceramic input
and output capacitors.
Charger Start-Up
When the charger is enabled, it will not begin switching
until the ITH voltage exceeds a threshold that assures initial
current will be positive. This threshold is 5% to 15% of the
maximum programmed current. After the charger begins
switching, the various loops will control the current at a
level that
is higher or lower than the initial current. The
duration of this transient condition depends upon the loop
compensation, but is typically less than 100µs.
Thermistor Detection
The thermistor detection circuit is shown in Figure 3. It
requires an external resistor and capacitor in order to
function properly.
The thermistor detector performs a sample-and-hold
function. An internal clock, whose frequency is determined
I
CHARGE
(% OF MAXIMUM CURRENT)
0
0
V
PROG
(V)
0.2
0.4
0.6
0.8
20 40
60 80
100
40071 F02
1.0
1.2 1.19V
0.309V
Figure 2. V
PROG
vs I
CHARGE

LTC4007EUFD-1#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management 4A, Hi Eff, Li-Ion Bat Chr
Lifecycle:
New from this manufacturer.
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