QT100-ISG Datasheet QT100-ISG | P4-P6

Figure 2.4 SYNC Mode (Short Pulses)

SNSK

QT100

SYNC

>10us >10us >10us

2.1.4 SYNC Mode

It is possible to synchronize the device to an external clock

source by placing an appropriate waveform on the SYNC pin.

SYNC mode can synchronize multiple QT100 devices to each

other to prevent cross-interference, or it can be used to

enhance noise immunity from low frequency sources such as

50Hz or 60Hz mains signals.

The SYNC pin is sampled at the end of each burst. If the

device is in Fast mode and the SYNC pin is sampled high,

then the device continues to operate in Fast mode

(Figure 2.2). If SYNC is sampled low, then the device

goes to sleep. From then on, it will operate in SYNC mode

(Figure 2.1). Therefore, to guarantee entry into SYNC

mode the low period of the SYNC signal should be longer

than the burst length (Figure 2.3).

However, once SYNC mode has been entered, if the

SYNC signal consists of a series of short pulses (>10µs)

then a burst will only occur on the leading edge of each

pulse (Figure 2.4) instead of on each change of SYNC

signal, as normal (Figure 2.3).

In SYNC mode, the device will sleep after each

measurement burst (just as in LP mode) but will be

awakened by a change in the SYNC signal in either

direction, resulting in a new measurement burst. If SYNC

remains unchanged for a period longer than the LP mode

sleep period (about 85ms), the device will resume

operation in either Fast or LP mode depending on the

level of the SYNC pin (Figure 2.3).

There is no DI in SYNC mode (each touch is a detection)

but the Max On-duration will depend on the time between

SYNC pulses; see Sections 2.3 and 2.4. Recalibration

timeout is a fixed number of measurements so will vary

with the SYNC period.

2.2 Threshold

The internal signal threshold level is fixed at 10 counts of

change with respect to the internal reference level, which

in turn adjusts itself slowly in accordance with the drift

compensation mechanism.

The QT100 employs a hysteresis dropout of two counts

of the delta between the reference and threshold levels.

2.3 Max On-duration

If an object or material obstructs the sense pad the signal

may rise enough to create a detection, preventing further

operation. To prevent this, the sensor includes a timer

which monitors detections. If a detection exceeds the

timer setting the sensor performs a full recalibration. This is

known as the Max On-duration feature and is set to ~80s (at

3V). This will vary slightly with Cs and if SYNC mode is used.

As the internal timebase for Max On-duration is determined by

the burst rate, the use of SYNC can cause dramatic changes

in this parameter depending on the SYNC pulse spacing.

2.4 Detect Integrator

It is desirable to suppress detections generated by electrical

noise or from quick brushes with an object. To accomplish

this, the QT100 incorporates a ‘detect integration’ (DI) counter

that increments with each detection until a limit is reached,

after which the output is activated. If no detection is sensed

prior to the final count, the counter is reset immediately to

zero. In the QT100, the required count is four. In LP mode the

device will switch to Fast mode temporarily in order to resolve

the detection more quickly; after a touch is either confirmed or

denied the device will revert back to normal LP mode

operation automatically.

The DI can also be viewed as a 'consensus' filter, that

requires four successive detections to create an output.

lQ 4 QT100_3R0.09_0707

Figure 2.1 Low Power Mode (SYNC held low)

SYNC

SNSK

QT100

sleepsleep sleep

fast detect

integrator

OUT

Key

touch

~85ms

Figure 2.2 Fast Mode Bursts (SYNC held high)

SNSK

QT100

SYNC

~1ms

Figure 2.3 SYNC Mode (triggered by SYNC edges)

SYNC

SNSK

QT100

SNSK

QT100

slow mode sleep period

sleep

sleepsleep

Revert to Fast Mode

Revert to Slow Mode

slow mode sleep period

2.5 Forced Sensor Recalibration

The QT100 has no recalibration pin; a forced

recalibration is accomplished when the device is

powered up or after the recalibration timeout.

However, supply drain is low so it is a simple

matter to treat the entire IC as a controllable load;

driving the QT100's V

DD pin directly from another

logic gate or a microcontroller port will serve as

both power and 'forced recal'. The source

resistance of most CMOS gates and

microcontrollers are low enough to provide direct

power without problem.

2.6 Drift Compensation

Signal drift can occur because of changes in Cx

and Cs over time. It is crucial that drift be

compensated for, otherwise false detections,

nondetections, and sensitivity shifts will follow.

Drift compensation (Figure 2.5). is performed by making the

reference level track the raw signal at a slow rate, but only

while there is no detection in effect. The rate of adjustment

must be performed slowly, otherwise legitimate detections

could be ignored. The QT100 drift compensates using a

slew-rate limited change to the reference level; the threshold

and hysteresis values are slaved to this reference.

Once an object is sensed, the drift compensation mechanism

ceases since the signal is legitimately high, and therefore

should not cause the reference level to change.

The QT100's drift compensation is 'asymmetric'; the reference

level drift-compensates in one direction faster than it does in

the other. Specifically, it compensates faster for decreasing

signals than for increasing signals. Increasing signals should

not be compensated for quickly, since an approaching finger

could be compensated for partially or entirely before even

approaching the sense electrode. However, an obstruction

over the sense pad, for which the sensor has already made

full allowance, could suddenly be removed leaving the sensor

with an artificially elevated reference level and thus become

insensitive to touch. In this latter case, the sensor will

compensate for the object's removal very quickly, usually in

only a few seconds.

With large values of Cs and small values of Cx, drift

compensation will appear to operate more slowly than with the

converse. Note that the positive and negative drift

compensation rates are different.

2.7 Response Time

The QT100's response time is highly dependent on run mode

and burst length, which in turn is dependent on Cs and Cx.

With increasing Cs, response time slows, while increasing

levels of Cx reduce response time. The response time will

also be a lot slower in LP or SYNC mode due to a longer time

between burst measurements.

2.8 Spread Spectrum

The QT100 modulates its internal oscillator by ±7.5 percent

during the measurement burst. This spreads the generated

noise over a wider band reducing emission levels. This also

reduces susceptibility since there is no longer a single

fundamental burst frequency.

2.9 Output Features

2.9.1 Output

The output of the QT100 is active-high upon detection. The

output will remain active-high for the duration of the detection,

or until the Max On-duration expires, whichever occurs first. If

a Max On-duration timeout occurs first, the sensor performs a

full recalibration and the output becomes inactive (low) until

the next detection.

lQ 5 QT100_3R0.09_0707

Figure 2.5 Drift Compensation

Threshold

Signal

Hysteresis

Reference

Output

Figure 2.7

Using a micro to obtain HeartBeat pulses in either output state

Figure 2.6

Getting HeartBeat pulses with a pull-up resistor

VDD

OUT

SNS

SYNC/MODE

SNSK

VSS

VDD

HeartBeat™ Pulses

Microcontroller

PORT_M.x

PORT_M.y

OUT

SNS

SYNC/MODE

SNSK

2.9.2 HeartBeat™ Output

The QT100 output has a HeartBeat™ ‘health’ indicator

superimposed on it in both LP and SYNC modes. This

operates by taking the output pin into a three-state mode for

15µs once before every QT burst. This output state can be

used to determine that the sensor is operating properly, or it

can be ignored, using one of several simple methods.

The HeartBeat indicator can be sampled by using a pull-up

resistor on the OUT pin, and feeding the resulting

positive-going pulse into a counter, flip flop, one-shot, or other

circuit. The pulses will only be visible when the chip is not

detecting a touch.

If the sensor is wired to a microcontroller as shown in

Figure 2.7, the microcontroller can reconfigure the load

resistor to either V

SS or VDD depending on the output state of

the QT100, so that the pulses are evident in either state.

Electromechanical devices like relays will usually ignore the

short Heartbeat pulse. The pulse also has too low a duty cycle

to visibly affect LEDs. It can be filtered completely if desired,

by adding an RC filter to the output, or if interfacing directly

and only to a high-impedance CMOS input, by doing nothing

or at most adding a small noncritical capacitor from OUT to

SS.

2.9.3 Output Drive

The OUT pin is active high and can sink or source up to 2mA.

When a large value of Cs (>20nF) is used the OUT current

should be limited to <1mA to prevent gain-shifting side effects,

which happen when the load current creates voltage drops on

the die and bonding wires; these small shifts can materially

influence the signal level to cause detection instability.

3 Circuit Guidelines

3.1 Application Note

Refer to Application Note AN-KD02, downloadable from the

Quantum website for more information on construction and

design methods. Go to http://www.qprox.com, click the

Support tab and then Application Notes.

3.2 Sample Capacitor

Cs is the charge sensing sample capacitor. The required Cs

value depends on the thickness of the panel and its dielectric

constant. Thicker panels require larger values of Cs. Typical

values are 2nF to 50nF depending on the sensitivity required;

larger values of Cs demand higher stability and better

dielectric to ensure reliable sensing.

The Cs capacitor should be a stable type, such as X7R

ceramic or PPS film. For more consistent sensing from unit to

unit, 5 percent tolerance capacitors are recommended. X7R

ceramic types can be obtained in 5 percent tolerance at little

or no extra cost. In applications where high sensitivity (long

burst length) is required the use of PPS capacitors is

recommended.

3.3 Power Supply, PCB Layout

The power supply can range between 2.0V and 5.5V. At 3V

current drain averages less than 500µA in Fast mode.

If the power supply is shared with another electronic system,

care should be taken to ensure that the supply is free of digital

spikes, sags, and surges which can adversely affect the

QT100. The QT100 will track slow changes in V

DD, but it can

be badly affected by rapid voltage fluctuations. It is highly

recommended that a separate voltage regulator be used just

for the QT100 to isolate it from power supply shifts caused by

other components.

If desired, the supply can be regulated using a Low Dropout

(LDO) regulator, although such regulators often have poor

transient line and load stability. See Application Note

AN-KD02 (see Section 3.1) for further information on power

supply considerations.

Parts placement: The chip should be placed to minimize the

SNSK trace length to reduce low frequency pickup, and to

reduce stray Cx which degrades gain. The Cs and Rs

resistors (see Figure 1.1) should be placed as close to the

body of the chip as possible so that the trace between Rs and

the SNSK pin is very short, thereby reducing the antenna-like

ability of this trace to pick up high frequency signals and feed

them directly into the chip. A ground plane can be used under

the chip and the associated discretes, but the trace from the

Rs resistor and the electrode should not run near ground to

reduce loading.

For best EMC performance the circuit should be made entirely

with SMT components.

Electrode trace routing: Keep the electrode trace (and the

electrode itself) away from other signal, power, and ground

traces including over or next to ground planes. Adjacent

switching signals can induce noise onto the sensing signal;

any adjacent trace or ground plane next to, or under, the

electrode trace will cause an increase in Cx load and

desensitize the device.

Important Note: for proper operation a 100nF (0.1µF)

ceramic bypass capacitor must be used directly between

DD and VSS, to prevent latch-up if there are substantial

DD transients; for example, during an ESD event. The

bypass capacitor should be placed very close to the

device’s power pins.

lQ 6 QT100_3R0.09_0707

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