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ADF4007BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Data Sheet ADF4007
Rev. B | Page 3 of 16
SPECIFICATIONS
AV
DD
= DV
DD
= 3 V ± 10%, AV
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 kΩ, dBm referred to 50 Ω,
T
A
= T
MAX
to T
MIN
, unless otherwise noted.
Table 1.
Parameter B Version
1
Unit Test Conditions/Comments
RF Input Frequency (RF
) 1.0/7.0 GHz min/max RF input level: +5 dBm to −10 dBm
RF Input Frequency 0.5/7.5 GHz min/max RF input level: +5 dBm to −5 dBm, for lower frequencies,
ensure that slew rate (SR) > 560 V/µs
REF
CHARACTERISTICS
REF
Input Sensitivity 0.8/V
DD
V p-p min/max Biased at AV
DD
/2
2
REF
Input Frequency 20/240 MHz min/max For f < 20 MHz, use square wave (slew rate > 50 V/µs)
REF
Input Capacitance 10 pF max
±100
µA max
PHASE DETECTOR
Phase Detector Frequency
3
120 MHz max
MUXOUT
MUXOUT Frequency
3
200 MHz max C
L
= 15 pF
CHARGE PUMP
I
Sink/Source 5.0 mA typ With R
SET
= 5.1 kΩ
Absolute Accuracy 2.5 % typ With R
SET
= 5.1 kΩ
R
Range 3.0/11 kΩ typ
I
Three-State Leakage 10 nA max T
A
= 85°C
Sink and Source Current Matching 2 % typ 0.5 V ≤ V
CP
≤ V
P
− 0.5 V
I
vs. V
1.5 % typ 0.5 V ≤ V
CP
≤ V
P
− 0.5 V
I
vs. Temperature 2 % typ VCP = V
P
/2
LOGIC INPUTS
V
, Input High Voltage 1.4 V min
V
, Input Low Voltage 0.6 V max
I
, I
, Input Current ±1 µA max T
A
= 25°C
C
, Input Capacitance 10 pF max
LOGIC OUTPUTS
V
, Output High Voltage V
DD
− 0.4 V min I
OH
= 100 µA
0.4
V max
I
OL
= 500 µA
POWER SUPPLIES
AV
2.7/3.3 V min/max
DV
AV
DD
V
AV
DD
/5.5 V min/max AV
DD
≤ V
P
≤
5.5 V
I
4
(AI
+ DI
) 17 mA max 15 mA typ
I
2.0 mA max T
A
= 25°C
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
5
−219 dBc/Hz typ
1
Operating temperature range (B version) is −40°C to +85°C.
2
AC coupling ensures AV
DD
/2 bias. See Figure 13 for typical circuit.
3
Guaranteed by design. Characterized to ensure compliance.
4
T
A
= 25°C; AV
DD
= DV
DD
= 3 V; N = 64; RF
IN
= 7.5 GHz.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN
TOT
, and subtracting 20logN (where N is the N divider
value) and 10logFPFD. PN
SYNTH
= PN
TOT
− 10logF
PFD
− 20logN. The in-band phase noise (PN
TOT
) is measured using the HP8562E Spectrum Analyzer from Agilent.
ADF4007 Data Sheet
Rev. B | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 2.
Parameter Rating
AV
DD
to GND
1
−0.3 V to +3.6 V
AV
DD
to DV
DD
−0.3 V to +0.3 V
V
P
to GND −0.3 V to +5.8 V
V
P
to AV
DD
−0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND −0.3 V to V
P
+ 0.3 V
REF
IN
, RF
IN
A, RF
IN
B to GND
−0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
CSP θ
JA
Thermal Impedance 122°C/W
Lead Temperature, Soldering
Vapor Phase (60 s) 215°C
Infrared (15 s) 220°C
Transistor Count
CMOS 6425
Bipolar 303
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
1
GND = AGND = DGND = 0 V.
Data Sheet ADF4007
Rev. B | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
14
13
12
1
3
4
M1
15 MUXOUT
M2
N1
11
N2
CPGND
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT
MUST BE CONNECTED TO GROUND.
AGND
2
AGND
RF
IN
B
5
RF
IN
A
7
AV
DD
6
AV
DD
8
REF
IN
9
DGND
10
DGND
19
R
SET
20
CP
18
V
P
17
DV
DD
16
DV
DD
TOP
VIEW
ADF4007
04537-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 CPGND Charge Pump Ground. The ground return path of the charge pump.
2, 3 AGND Analog Ground. The ground return path of the prescaler.
4 RF
IN
B Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
5 RF
IN
A Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
6, 7 AV
DD
Analog Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV
DD
must be the same value as DV
DD
.
8 REF
IN
Reference Input. A CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input resistance of 100 kΩ.
This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9, 10 DGND Digital Ground.
11, 12 N2, N1 These two bits set the N value. See Table 4.
13, 14 M2, M1 These two bits set the status of MUXOUT and PFD polarity. See Table 5.
15 MUXOUT This multiplexer output allows either the N divider output or the R divider output to be accessed externally.
16, 17 DV
DD
Digital Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
18
V
P
Charge Pump Power Supply. This pin should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it can be
set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
19 R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal
voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
SET
MAXCP
R
I
5.25
=
Therefore, if R
SET
= 5.1 kΩ, then I
CP
= 5 mA.
20
CP
Charge Pump Output. When enabled, this pin provides ±I
CP
to the external loop filter, which in turn drives the
external VCO.
21 EP Exposed Pad.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ADF4007BCPZ

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Buy ADF4007BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL High Freq Divider/ Synthesizer
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