1997 Apr 16 6
Philips Semiconductors Product specification
4-digit duplex LCD car clock PCF1175C
12/24-hour mode
Operation in 12-hour or 24-hour mode is selected by
connecting MODE to V
DD
or V
SS
respectively. If MODE is
left open-circuit and a reset occurs, the mode will change
from 12-hour to 24-hour mode or vice versa.
Power-on
After connecting the supply, the start-up mode is:
MODE connected to V
DD
: 12-hour mode, 1:00 AM.
MODE connected to V
SS
: 12-hour mode, 0:00.
MODE left open-circuit: 24-hour mode, 0:00 or 1:00.
Colon
If FLASH is connected to V
DD
the colon pulses at 1 Hz.
If FLASH is connected to V
SS
the colon is static.
Time setting
Switch inputs S1 and S2 have a pull-up resistor to facilitate
the use of single-pole, single-throw contacts. A debounce
circuit is incorporated to protect against contact bounce
and parasitic voltages.
Set enable
Inputs S1 and S2 are enabled by connecting ENABLE to
V
DD
or disabled by connecting to V
SS
.
Set hours
When S1 is connected to V
SS
the hours displayed
advances by one and after one second continues with one
advance per second until S1 is released (auto-increment).
Set minutes
When S2 is connected to V
SS
the time displayed in
minutes advances by one and after one second continues
with one advance per second until S2 is released
(auto-increment). In addition to minute correction, the
seconds counter is reset to zero.
Segment test/reset
When S1 and S2 are connected to V
SS
, all LCD segments
are switched ON. Releasing switches S1 and S2 resets the
display. No reset occurs when DATA is connected to V
SS
(overlapping S1 and S2).
Test mode
When TS is connected to V
DD
, the device is in normal
operating mode. When connecting TS to V
SS
all counters
(seconds, minutes and hours) are stopped, allowing quick
testing of the display via S1 and S2 (debounce and
auto-increment times are 64 times faster). TS has a
pull-up resistor but for reasons of safety it should be
connected to V
DD
.
EEPROM
V
PP
has a pull-up resistor but for reasons of safety it should
be connected to V
DD
.
LCD voltage programming
To enable LCD voltage programming, SEL is set to
open-circuit and a level of V
DD
− 5 V is applied to V
PP
(see
Fig.6). The first pulse (t
E
) applied to the DATA input clears
the EEPROM to give the lowest voltage output. Further
pulses (t
L
) will increment the output voltage by steps of
typically 150 mV (T
amb
=25°C). For programming,
measure V
DD
− V
SS
and apply a store pulse (t
W
) when the
required value is reached. If the maximum number of steps
(n = 31) is reached and an additional pulse is applied the
voltage will return to the lowest value.
Time calibration
To compensate for the tolerance in the quartz crystal
frequency which has been positively offset (nominal
deviation +60 × 10
−6
) by capacitors at the oscillator input
and output, a number (n) of 262144 Hz are inhibited every
second of operation.
