AD824 Data Sheet
THEORY OF OPERATION
INPUT CHARACTERISTICS
In the AD824, n-channel JFETs are used to provide a low offset,
low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below −V
S
to 1 V
less than +V
S
. Driving the input voltage closer to the positive
rail causes a loss of amplifier bandwidth.
The AD824 does not exhibit phase reversal for input voltages up
to and including +V
S
. Figure 30a shows the response of an
AD824 voltage follower to a 0 V to 5 V (+V
S
) square wave input.
The input and output are superimposed. The output tracks the
input up to +V
S
without phase reversal. The reduced bandwidth
above a 4 V input causes the rounding of the output waveform.
For input voltages greater than +V
S
, a resistor in series with the
noninverting input prevents phase reversal at the expense of
greater input voltage noise. This is illustrated in Figure 30b.
10
0%
100
90
1V
1V
10µs1V
10
0%
100
90
1V
2µs
1V
GND
GND
+V
S
5V
R
P
V
OUT
V
IN
(b)
(a)
00875-030
Figure 30. (a) Response with R
P
= 0; V
IN
from 0 V to +V
S
;
(b) V
IN
= −200 V to + V
S
+ 200 mV; V
OUT
= 0 V to + V
S
; R
P
= 49.9 kΩ
Because the input stage uses n-channel JFETs, input current
during normal operation is positive; the current flows out from
the input terminals. If the input voltage is driven more positive
than +V
S
− 0.4 V, the input current reverses direction as internal
device junctions become forward biased. This is illustrated in
Figure 10.
Use a current-limiting resistor in series with the input of the
AD824 if there is a possibility of the input voltage exceeding the
positive supply by more than 300 mV or if an input voltage will
be applied to the AD824 when ±V
S
= 0 V. The amplifier will be
damaged if left in that condition for more than 10 seconds. A
1 kΩ resistor allows the amplifier to withstand up to 10 V of
continuous overvoltage and increases the input voltage noise by
a negligible amount.
Input voltages less than −V
S
are a completely different story. The
amplifier can safely withstand input voltages 20 V below the
−V
S
as long as the total voltage from the +V
S
to the input termi-
nal is less than 36 V. In addition, the input stage typically maintains
picoamp level input currents across that input voltage range.
OUTPUT CHARACTERISTICS
The unique bipolar rail-to-rail output stage of the AD824
swings within 15 mV of the positive and negative supply
voltages. The approximate output saturation resistance of the
AD824 is 100 Ω for both sourcing and sinking. This can be used
to estimate output saturation voltage when driving heavier
current loads. For instance, the saturation voltage is 0.5 V from
either supply with a 5 mA current load.
For load resistances over 20 kΩ, the input error voltage of the
AD824 is virtually unchanged until the output voltage is driven
to 180 mV of either supply.
If the output of the AD824 is overdriven to saturate either of the
output devices, the amplifier will recover within 2 μs of its input
returning to the amplifier’s linear operating region.
Direct capacitive loads will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. Figure 6 and Figure 8 show the
pulse response of the AD824 as a unity gain follower driving
220 pF. Configurations with less loop gain, and as a result less
loop bandwidth, will be much less sensitive to capacitance load
effects. Noise gain is the inverse of the feedback attenuation
factor provided by the feedback network in use.
Figure 31 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component
values, the circuit drives 5,000 pF with a 10% overshoot.
1/4
AD824
8
4
V
IN
+V
S
–V
S
V
OUT
20pF
20kΩ
C
L
0.01µF
0.01µF
100Ω
00875-031
Figure 31. Extending Unity Gain Follower Capacitive Load Capability
Beyond 350 pF
Rev. E | Page 12 of 16
