NCP4352
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7
APPLICATION INFORMATION
A typical application circuits for NCP4352 series is
shown in Figure 19. Pin functions are available in pin
description table.
Figure 20 shows possible connection to flyback primary
controller. This schematic uses one single optocoupler for
both voltage and current regulation functions.
Those schematics provide all possible functionalities.
Power Supply
The NCP4352 is designed to operate from a single supply
up to 36 V. It starts to operate when VCC voltage reaches
3.5 V and stops when VCC voltage drops below 2.5 V. VCC
can be supplied by direct connection to the VOUT voltage
of the power supply. It is recommended to add a RC filter
(R1 and C3) in series from VOUT to VCC pin to reduce
voltage spikes and drops that are produced at the converter’s
output capacitors. Recommended values for this filter are
220 Ω and 1 mF.
Voltage Regulation Path
The output voltage is detected on the VSNS pin by the R3
and R4 voltage divider. This voltage is compared with the
internal precise voltage reference. The voltage difference is
amplified by gm
V
of the transconductance amplifier. The
amplifier output current is connected to the FBC pin. The
compensation network is also connected to this pin to
provide frequency compensation for the voltage regulation
path. This FBC pin drives an optocoupler to prove the
secondary side regulation. The optocoupler is supplied via
direct connection to VOUT line through resistor R1.
Regulation information is transferred through the
optocoupler to the primary side controller where its FB pin
is usually pulled down to reduce energy transferred to
secondary output.
The output voltage can be computed by Equation 1.
V
OUT
+ V
REF
R3 ) R4
R4
(eq. 1)
Current Regulation Path
The output current is sensed by the shut resistor R11 in
series with the load. Voltage drop on R11 is compared with
internal precise voltage reference V
REFC
at ISNS
transconductance amplifier input.
Voltage difference is amplified by gm
C
to output current
of amplifier, connected to FBC pin. Compensation network
is connected between this pin and ISNS input to provide
frequency compensation for current regulation path.
Current regulation OTA is activated only in normal mode,
during ECO mode is turned−off to save energy. It doesn’t
make any issue, because ECO mode is activated just in case
of light load so current regulation path is not needed.
Current regulation point is set to current given by
Equation 2.
I
OUTLIM
+
V
REFC
R11
(eq. 2)
ECO Mode Detection
ECO mode operation is advantageous for ultra low output
current condition. The reduced output voltage with very
long skip off time and the low power mode of the whole
regulation system reduces strongly the overall consumption.
The output voltage is reduced to a second regulation point
in ECO mode. When output voltage decreases, the overall
output and regulation power are reduced.
The ECO mode detection is based on comparison of
output voltage and voltage loaded with fixed resistances
(D2, R6, R7, R8 and C2).
Figure 21 shows detection waveforms. When output
voltage is loaded with very low current, primary controller
goes into skip mode (primary controller stops switching for
some time). While output power is reduced, thanks to the
serial resistance R6, the voltage on capacitor C2 provides a
voltage proportional to output power, allowing power level
detection.
Ones ECODET pin voltage goes lower than V
ECODETTH
(this threshold is derived from V
OUT
= V
CC
), ECO mode is
detected. This means that ECO mode is not activated until
falling edge comes at ECODET pin.
To reduce output voltage on C1 down to the new
regulation point, the current I
BIASV
injected into VSNS pin
provides the requested offset (VSNS voltage is higher than
V
REF
). This offset, defined by R4, R5 and the internal
current source, allows keeping the same output voltage
resistances divider defined for the normal mode. Reduced
output voltage in ECO mode can be computed by
Equation 3.
I
R3
+
V
REF
) (R4 ) R5) @ I
BIASV
R4
(eq. 3)
V
OUT_ECO
+ I
R3
@ R3 )
ǒ
I
R3
* I
BIASV
Ǔ
@ R4
The sink current on primary FB pin is so adjusted to keep
primary controller FB in line with the new working point
with reduced output voltage.
Primary IC should be kept supplied from auxiliary
winding of the transformer despite overall voltage
reduction. This may ask for serial voltage regulator to avoid
over voltage in normal mode.
If output power increases such that ECODET pin voltage
is higher than 10% of V
CC
, the ECO mode is ended and
regulation is switched back to original normal mode. The IC
also starts in normal mode after UVLO event.
